Patents Examined by Michael T. Richey
  • Patent number: 5787488
    Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for application to each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: July 28, 1998
    Assignee: Analog Devices, Inc.
    Inventor: Douglas Garde
  • Patent number: 5781779
    Abstract: To generate computationally efficient computer program code for carrying out computer computations on matrix organized input data, a program first is written in a relatively high-level language which includes programmer specifiable constructs for manipulating matrices and parts thereof; and which permits certain of the constructs to be annotated to specify programmer selected data structures and programmer selected operations on those data structures. This high-level program then is translated into a relatively high-level program into a relatively low-level language using low-level language routines that provide a compilable representation of the program, including all programmer selected data structures and all programmer selected operations on said data structures then the low-level representation of the program is compiled to generate computer executable code for implementing the program, including all programmer selected data structures and all programmer selected operations on said data structures.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: July 14, 1998
    Assignee: Xerox Corporation
    Inventors: John R. Gilbert, John O. Lamping, Anurag Mendhekar, Tatiana Shpeisman
  • Patent number: 5781778
    Abstract: A debugger client/server application comprising a front-end and one or more back-ends, including a Director component which handles most of the initialization and parallel execution control issues and a rp.sub.-- client component and rp.sub.-- server component which handles most of the distributed execution issues. The Director allows a Debug Engine to be unaware of most of the parallel and distributed aspects of the application. Thus, the Debug Engine can be created by re-using a serial debugger for presenting the state information about the various programs that make up the application.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: July 14, 1998
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Meier, Hsin Pan
  • Patent number: 5778227
    Abstract: The system uses an intermediary process in an object oriented computer environment to allow application objects to perform operations such as creation, deletion and accessing of other objects. Typically the other objects are database objects. The intermediary process allows associations to be made between add-on attributes and primary objects. The primary objects are objects that are designed to be used by an original application. A later application that wishes to use the same objects as the original application, but with additional attributes, can create, delete and access the additional attributes at run time so that extra functionality is provided to a user of the original application program in an efficient manner.
    Type: Grant
    Filed: August 1, 1995
    Date of Patent: July 7, 1998
    Assignee: Intergraph Corporation
    Inventor: David A. Jordan
  • Patent number: 5768584
    Abstract: A non-volatile memory chip enable encoding method allows the storage of both boot code and user application software within a common memory array. The chip enable encoding method further allows a variable number of memory banks to be provided within the non-volatile memory array and allows the system to power-up and execute the boot code before the array configurations are selected by firmware. In one embodiment, a memory controller includes four chip enable output lines for selectively enabling a plurality of ROM banks. One of the ROM banks includes boot code that is executed by the system microprocessor during system boot. If the user requires a ROM array consisting of four ROM banks, a separate chip enable output line is connected to each ROM bank. If the user instead requires a ROM array consisting of, for example, eight ROM banks, an external decoder may be connected to the four chip enable output lines.
    Type: Grant
    Filed: September 10, 1996
    Date of Patent: June 16, 1998
    Assignee: Advanced Micro Systems, Inc.
    Inventors: James R. MacDonald, Douglas D. Gephardt
  • Patent number: 5764982
    Abstract: A method and system for generating symmetrical communication interfaces using asymmetrical tools defines two interface definition files. The two interface definition files are compiled by an interface definition compiler to create first role and second role interface files, such as client and server roles for two symmetrical replicas. The first role interface file resulting from the compile of the first interface definition file is discarded, while the second role interface file resulting from the compile of the second interface definition file is also discarded. The first role interface file resulting from the compile of the second interface definition file and the second role interface file resulting from the compile of the first interface definition file are replicated in a plurality of systems coupled to the network.
    Type: Grant
    Filed: August 11, 1994
    Date of Patent: June 9, 1998
    Assignee: International Business Machines Corporation
    Inventor: Hari Haranath Madduri
  • Patent number: 5761509
    Abstract: A system for creating before and after behavior upon invocation of a method in an object-oriented system. The framework provides metaclasses containing methods for dispatching a before method and an after method at the time of invocation of each client method in subclass instances. Object-oriented system properties of inheritance and encapsulation are supported as are derived metaclasses. Derivation ensures that the specification syntax for each class does not impact the expected result. The combination of explicit before after classes, dispatcher class, and derived metaclasses ensures that the system will have associative composition.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Scott Harrison Danforth, Ira Richard Forman, Hari Haranath Madduri
  • Patent number: 5761079
    Abstract: A system for identifying and bounding the regions of a digital electronic logic design model that are affected by design revisions. The system is useful for improving the efficiency of incremental logic synthesis systems and includes procedures for recording the signals directly affected by user revision operations and for marking signals in the logic to identify those indirectly affected. A smart editor capable of parsing the formal register transfer language (RTL) in which the logic design is described is included in the system.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventor: Anthony DeGroff Drumm
  • Patent number: 5758340
    Abstract: The present invention is a data processing system and method for providing controlled, multi-tiered checkout of a subset of a first data model storage (111) to a second data model storage (111). The present invention include a checkout module (107) responsive to a user checkout request and a first protection level associated with the first data model storage (111) for generating a subset of the first data model storage (111), for generating a second protection level associated with the subset, for updating the first protection level in accordance with the second protection level, and for updating a second data model storage (111) with the subset and the second protection level associated with the subset. The present invention also includes a data manager (108) for managing the subsetted data in accordance with the second protection level.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: May 26, 1998
    Assignee: Sterling Software, Inc.
    Inventor: Jill Nail
  • Patent number: 5752036
    Abstract: In a printer driver 11, a source code for an image processing procedure called out by an application program 12 is generated. A grain size detection process 48 counts the number of procedures which have been called out and a parallelization position detection process 49 checks whether each procedure called out is attended with pixel generation or not and whether the procedure depends on the preceding procedure or not. While calling-out of procedures not dependent on the preceding procedure is continued, source codes for those procedures are accumulated in a buffer 60. Whenever a procedure attended with pixel generation is called out, the printer driver 11 outputs a set of source codes accumulated in the buffer 60 in a description of a complex sentence indicating a parallel processing unit in accordance with the grammar of a parallel sentence structure as long as the aforementioned count value reaches the grain size of a preliminarily set unit of parallel processing.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: May 12, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Eri Nakamura, Fumio Nagasaka
  • Patent number: 5751943
    Abstract: An electronic work environment for a data processing system includes documentation modules which execute on the hardware elements of the system. The documentation modules exchange data between the software elements and hardware elements of the data processing system to produce interaction between the documentation modules and the data processing system. A common user interface module displays the results of the interaction between the software and hardware elements and the documentation modules. Accordingly, the documentation becomes part of the operating environment of the data processing system. The documentation modules are generalized documentation modules including online documentation for every possible configuration of the hardware and software elements of the data processing system.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: May 12, 1998
    Assignee: Alcatel Network Systems, Inc.
    Inventors: Craig Kay Benzenberg, Lloyd Steven Mann, Lawrence Carl Oslund, Colleen Ann Roe
  • Patent number: 5748963
    Abstract: The invention includes an efficient method of dynamically binding an operation (22) to an implementation. During a first occurrence of the operation, the operation identifier and argument information are compared with entries (52) in a dictionary (50) to determine an appropriate implementation. The operation is modified by replacing the operation identifier (58) and argument information (60) with a reference to a matching entry (52). Upon subsequent execution of the operation, the interpreter checks to see whether the types of the arguments in the current function call match those in the dictionary entry. If they match, the implementation referenced by the dictionary entry is executed. If they do not match, the dictionary is searched for a matching entry. Because most operations do not change types of arguments during most function calls, the invention results in greatly improved efficiency.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: May 5, 1998
    Assignee: Design Intelligence, Inc.
    Inventor: Michael B. Orr
  • Patent number: 5742830
    Abstract: A Structured External Storage (SES) processor is linked by a communication means to one or more general purpose processors. Two or more applications executing on the one or more general purpose processors communicate function request messages to a message processor within the SES to effect serialized sharing of data within the SES. Within the message processor, a predicate function means executes unconditionally on receipt of one of the function request messages, and a data function means executes conditionally and atomically with respect to the predicate function means following a "successful" condition produced by the predicate function means.
    Type: Grant
    Filed: February 1, 1995
    Date of Patent: April 21, 1998
    Assignee: International Business Machines Corporation
    Inventors: David Arlen Elko, Jeffrey Alan Frey, Audrey Ann Helffrich, John Franklin Isenberg, Jr., Jeffrey Mark Nick, Jimmy Paul Strickland, Michael Dustin Swanson, Brian Barry Moore
  • Patent number: 5729746
    Abstract: A computerized interactive tool for developing a software product that provides estimates of the final lines of code of the software product at several points during the software development process to properly allocate programming effort resources. The estimates converge with actual results as the software development process progresses from one phase to the next.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: March 17, 1998
    Inventor: Ricky Jack Leonard
  • Patent number: 5717909
    Abstract: A computer with a pipelined processor and code breakpoints for performing software debug operations includes prefetch and decode stages, debug address registers for storing code breakpoints representing addresses of preselected instructions, and two digital comparators. During the instruction prefetch phase of operation, the first comparator compares the 29 most significant bits ?31:3! of the 32-bit prefetch instruction address against the code breakpoints stored in the debug address registers and produces a 1-bit signal indicating whether such comparison results in a positive match. Subsequently, during the decode phase of operation, the second comparator compares the three least significant bits ?2:0! of the 32-bit prefetch instruction address and produces a 1-bit signal indicating whether such comparison results in a positive match.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: February 10, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Mario D. Nemirovsky, Robert James Divivier, Robert Walter Williams
  • Patent number: 5717930
    Abstract: The present invention provides an installation system that facilitates the operation on computer terminals in the network system and allows for automatic installation of an operating system software program on computer terminals. A PC to be shipped is connected to a network. After the PC is switched on, an installation floppy disk is inserted in the drive and started up. The installation start-up program stored in the floppy disk is copied to the internal memory of the PC. After the PC is connected to an installation server, the hard disk drive is initialized. The bar coded ID of the PC is read with a bar code reader. The installation information relevant to that ID is retrieved from the installation server by using the ID as a key.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: February 10, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Tsuneo Imai, Yoshifumi Mitani, Kiyoharu Komatsu
  • Patent number: 5706516
    Abstract: Data processing application requests are processed in a computer system configured as a plurality of nodes with a plurality of interacting processes. Data is requested by an application request originating on a first node. The request data includes data located on a plurality of the nodes. A portion of computer memory on the nodes is established as agent message queues ("AMQ's"). A first process, acting as a coordinating agent, receives an application request on the first node. The coordinating agent generates a plurality of internal requests for the application request. The coordinating agent communicates the internal requests to a fast communication manager process ("FCM") on the first node. The first FCM, sends the internal requests to FCM's on the nodes having the request data ("request data nodes"), for storage in selected AMQ's on the request data nodes. The internal requests are retrieved from the selected AMQ's by processes acting as subordinate agents on the request data nodes.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: January 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: David Yu Chang, Marc Gregory Smith
  • Patent number: 5696914
    Abstract: This invention concerns an interactive interface description tool that uses an interpreted language in which both the data and the programs have a similar representation, This tool also has an interpreter that is embedded with the interface description program, This interpreter consists of a mixture of "C" language and interpreted language instructions and uses a library ("X/MOTIF") of interactive command objects ("widget") and a library of graphical objects ("GO").
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: December 9, 1997
    Assignee: Bull S.A.
    Inventors: Colas Nahaboo, Vincent Bouthors
  • Patent number: 5694601
    Abstract: A system and method is shown for enabling a plurality of computers and associated computer resources, some or all of which may be of heterogeneous configuration, to cooperatively process various applications such that the execution is transparent to the user regardless of where the application is actually executing. This distributed applications architecture performs an information distribution service between multiple transaction processing systems by working with a transaction processor via communication channels to other hosts within the network and a dialog manager which uses a transaction processor interface to communicate with the transaction processor. The architecture employs a map service which provides an editor to create the maps for the application panels, a compiler to generate the maps into a linkable form, and a linkable interpreter which translates the linkable form into the screen presentation format for that platform.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 2, 1997
    Assignee: Sterling Software, Inc.
    Inventor: John W. White
  • Patent number: 5680622
    Abstract: A development system having a compiler, a linker, and an interface is described. The compiler, which generates or "compiles" source listings into object modules, includes a parser for parsing information. Parsed information, which is initially stored in a parse tree, is further processed. A hash table is initialized for storing a unique address or signature for a particular data object (or set) of the tree. The nodes of the parse tree are processed in a "preorder" traversal. If a node under examination is not stored in the hash table, it is installed in the table and its address (hash address) is returned for storage in the tree. Other nodes of the tree are (recursively) processed in a similar manner. Two identical trees encountered in a parse will hash to the same address and thus need only be stored once. If two trees differ by only a small amount, only the difference and the left edge of the second tree will be stored in addition to the first.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: October 21, 1997
    Assignee: Borland International, Inc.
    Inventor: Lindsay Wayne Even