Abstract: A level shifter (1) that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. Level shifter (1) may include a transistor (P101) providing a controllable current path between a voltage terminal (3) and an output signal (TOUT) based on the logic level of an input signal (IN). Series connected transistors (P104 and P105) may provide a controllable current path between voltage terminal (3) and output signal (TOUT) based on the logic level of an input signal (IN). Transistor (P105) may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width (WT) may be adjusted in accordance with a mode of operation and a transition time of output signal (TOUT) may be improved.

Abstract: A low-cost, novel electrically erasable programmable read only memory cell array. The EEPROM memory cell array includes a well of P− type conductivity. A first well of N-type conductivity resides within the well of P− type conductivity. A second well of N-type conductivity residing within the well of P− type conductivity spaced apart from the first well of N-type conductivity. A plurality of wells of P+ type conductivity reside within the second well of N-type conductivity. A plurality of contacts coupling a plurality of bit lines to the plurality of wells of P+ type conductivity. A third well of N-type conductivity resides within the well of P− type conductivity and is spaced apart from the first well of N-type conductivity and the second well of N-type conductivity. A single polysilicon layer disposed over the first well, the second well, and the third well.