Abstract: After gates are patterned in a submicron CMOS process, a halo implant is performed with sufficient energy that the halo implant penetrates the gate structures to below the transistor channel regions. Where the substrate is not masked by gate materal, the halo implant penetrates below drain and source regions. During diffusion, this halo limits lateral diffusion of the source/drain dopants. The resulting transistor exhibits enhanced breakdown voltage characteristics during both on and off conditions.
March 31, 1994
Date of Patent:
March 7, 1995
VLSI Technology, Inc.
K. S. Ravindhran, Yu P. Han, Ravi Jhota, Walter D. Parmantie
Abstract: In the fabrication of VLSI circuits, the diffusion barrier layer on the pad areas are removed prior to the formation of metal layer. Metal layer on the pad areas are thus directly contact with the underlying SiO.sub.2 layer, thereby improving the pad bonding yield.
Abstract: A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.