Patents Examined by Michale A. Whitfield
  • Patent number: 5274596
    Abstract: A dynamic semiconductor device includes a plurality of dynamic memory cell arrays each having memory cells arranged in a matrix form, row decoders connected to the plurality of memory cell arrays, respectively, sense amplifiers connected to the plurality of memory cell arrays, respectively, a plurality of bit lines connected to the each of the plurality of memory cell arrays, for exchanging data with the memory cells arranged in the matrix form, the plurality of bit lines being connected to a corresponding one of the sense amplifiers, a plurality of word lines, intersecting the plurality of bit lines, for selecting the memory cells, the word lines selected by row addresses adjacent on a logical address plane being located in adjacent ones of the memory cell arrays, the word lines within the each memory cell array being selected by an upper row address of a row address output from a corresponding one of the row decoders, and means for selecting the memory cell arrays by a lower row address of the row address,
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: December 28, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yohji Watanabe