Abstract: In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that vary along the length of the gate and the problem of overetch of the STI oxide during the preclean step is solved by using a sacrificial nitride layer to block both the STI region and the gate stack, together with a process sequence in which the halo and extension implants are performed after the S/D implant anneal.
Type:
Grant
Filed:
June 20, 2001
Date of Patent:
August 6, 2002
Assignee:
International Business Machines Corporation
Inventors:
Heemyong Park, Fariborz Assaderaghi, Dominic J. Schepis