Patents Examined by Michelle Fan
  • Patent number: 9793435
    Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 17, 2017
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Robert M. Farrell, Jr., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh K. Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 8809079
    Abstract: The present teachings provide methods for forming organic layers for an organic light-emitting device (OLED) using an inkjet printing or thermal printing process. The method can further use one or more additional processes, such as vacuum thermal evaporation (VTE), to create an OLED stack. OLED stack structures are also provided wherein at least one of the charge injection or charge transport layers is formed by an inkjet printing or thermal printing method at a high deposition rate. The structure of the organic layer can be amorphous, crystalline, porous, dense, smooth, rough, or a combination thereof, depending on deposition parameters and post-treatment conditions. An OLED microcavity is also provided and can be formed by one of more of the methods.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: August 19, 2014
    Assignee: Kateeva, Inc.
    Inventors: Jianglong Chen, Ian Millard, Steven Van Slyke, Inna Tregub, Conor Madigan
  • Patent number: 8309429
    Abstract: A plurality of single crystal semiconductor substrates are arranged and then the plurality of single crystal semiconductor substrates which have been arranged are overlapped with a base substrate, so that the base substrate and the plurality of single crystal semiconductor substrates are bonded to each other. Then, each of the plurality of single crystal semiconductor substrates is separated to form a plurality of single crystal semiconductor layers over the base substrate. Next, in order to reduce crystal defects in the plurality of single crystal semiconductor layers, the plurality of single crystal semiconductor layers are irradiated with a laser beam. The plurality of single crystal semiconductor layers are thinned by being etched before or after irradiation with a laser beam.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: November 13, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8021958
    Abstract: A method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced is provided. An oxide film containing halogen is formed on each of surfaces of a single crystal semiconductor substrate and of a semiconductor substrate provided with a single crystal semiconductor layer separated from the single crystal semiconductor substrate, whereby impurities that exist on the surfaces of and inside the substrates are decreased. In addition, the single crystal semiconductor layer provided over the semiconductor substrate is irradiated with a laser beam, whereby crystallinity of the single crystal semiconductor layer is improved and planarity is improved.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: September 20, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eriko Nishida, Takashi Shimazu
  • Patent number: 7955961
    Abstract: A trench-type Schottky semiconductor device and a method for fabricating the trench-type Schottky semiconductor device are disclosed. The method includes the steps of forming an epitaxial (EPI) layer atop a silicon substrate, forming a nitride layer atop the EPI layer, patterning a plurality of windows in the nitride layer into an active region and a termination region, forming a plurality of trenches in the active and termination regions such that the plurality of trenches in the termination regions are spaced apart from each other so as to form a plurality of mesas, lining the first type of trenches with a gate oxide layer, and converting the mesas to oxide mesas; and then applying a barrier layer metal to the mesas in the device active area and in the termination trenches.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: June 7, 2011
    Assignee: International Rectifier Corporation
    Inventor: Giovanni Richieri