Abstract: A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.

Abstract: A method for migrating data by a source network interface card includes: receiving a first migration instruction; sending a read instruction to the source SSD when receiving the first migration instruction, where the read instruction is used to instruct the source SSD to read the to-be-migrated data into the source migration cache; and sending a second migration instruction to a target intelligent network interface card of the target storage array after the to-be-migrated data is read from the source SSD, where the second migration instruction is used to instruct the target intelligent network interface card to migrate the to-be-migrated data in the source migration cache to the target storage array.

Abstract: A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.

Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

Abstract: Intelligent storage of messages is provided. A spill-over page set is selected to store received messages corresponding to a predefined target page set associated with an application workload in response to the predefined target page set reaching a predefined minimum unused page threshold level. The spill-over page set is utilized as a message storage destination for the received messages corresponding to the predefined target page set associated with the application workload to extend message storage for the predefined target page set after the predefined target page set reached the predefined minimum unused page threshold level.

Abstract: A data storage device and method for providing an adaptive data path are disclosed. In one embodiment, a data storage device is in communication with a host comprising a first processor (e.g., a graphics processing unit (GPU)), a second processor (e.g., a central processing unit (CPU)), and a queue. The data storage device chooses a data path to use to communicate with the queue based on whether the queue is associated with the first processor or with the second processor. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

Abstract: Systems and methods for managing access to a block device. An example method includes receiving, by a processing device from an entity operating in a cloud-computing environment, a memory access command referencing a block device of a distributed storage system that is accessible by a plurality of entities of the cloud computing environment; identifying a data structure associated with the referenced block device, wherein the data structure identifies entities of the cloud-computing environment that are allowed access to the block device; determining, in view of the data structure, whether the entity is allowed access to the block device by the memory access command; and responsive to determining that the entity is allowed access to the block device by memory access command, executing the memory access command.

Abstract: Systems, methods, and non-transitory computer-readable media for providing a cloud storage device implementing C-ZNS architecture. The cloud storage device including a housing and a plurality of blades, with at least one blade including a plurality of storage devices and an electronic processor. The electronic processor is configured to receive data and a command from a host application to write the data to a corresponding zone of a first storage device of the plurality of storage devices, initialize a buffer in response to receiving the data, store the data in the buffer that is initialized, determine one or more parameters in response to receiving the command, determine that the command is error-free based on the one or more parameters, and write the data from the buffer into the corresponding zone in response to determining that the command is error-free.

Abstract: First and second target controllers implemented in a storage system are associated with respective first and second storage pools having respective first and second service level objectives. Input-output (IO) operations are received from one or more host devices and processed in the storage system, with different ones of the IO operations being directed from one or more initiators of the one or more host devices to different ones of the first and second target controllers. Separate feedback information is provided from the storage system to the one or more host devices for respective ones of the first and second target controllers, so as to permit different amounts of throttling of additional IO operations in the one or more host devices based at least in part on whether those additional IO operations are to be directed to the first target controller or the second target controller.

Abstract: A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

Abstract: Disclosed herein is an information processing device including a host unit adapted to request data access by specifying a logical address of a secondary storage device, and a controller adapted to accept the data access request and convert the logical address into a physical address using an address conversion table to perform data access to an associated area of the secondary storage device, in which an address space defined by the address conversion table includes a coarsely granular address space that collectively associates, with logical addresses, physical addresses that are in units larger than those in which data is read.

Abstract: Methods and systems for solid state drives are provided, including assigning a first shared namespace to a first instance and a second instance of a storage operating system for enabling write access to the first instance to a first zone of a first portion of a flash storage system, and write access to the second instance to a second zone of the first portion; using a first exclusive namespace by the first instance to store metadata at a first segment of a second portion of the flash storage system; using a second exclusive namespace by the second instance to store metadata at a second segment of the second portion of the flash storage system; and providing read only access to the first instance and the second instance to a second zone of the first portion using the first namespace.

Abstract: Methods, systems, and devices for power mode control in a multi-memory device are described. An apparatus may include a non-volatile memory and a volatile memory. The apparatus may operate the volatile memory in a first power mode and the non-volatile memory in a second power mode. The apparatus may transition the volatile memory from the first power mode to a third power mode based on a power mode command from a host device. The apparatus may transition the non-volatile memory from the second power mode to a fourth power mode that consumes less power than the second power mode irrespective of the command from the host device and based on a quantity of queued commands for the non-volatile memory being less than a threshold quantity.

Abstract: Storage object groups uniquely associated with respective host applications are processed to model, for each host application, the relationship between current utilized storage capacity of each host application and greatest possible utilized storage capacity of each host application without exhausting either the storage capacity of the storage system or the performance capacity of the storage system. The modeled relationships may be used to calculate headroom and performance impact scores for each host application. Storage object groups that have insufficient headroom for growth, e.g., as indicated by performance impact score, are deemed to be associated with host application workloads that are candidates for migration to a different storage system. The candidates may be ranked and selected for migration based on performance impact scores.

Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Transmission of data for object storage, such as stream transmission for object storage, is disclosed. For instance, a group of objects acquired from an object layer is stored in a storage space for storing an object stream and serves as a first part of the object stream; and, in response to that an event related to at least one object in the group of objects occurs at a client terminal, the event-related information is stored in the storage space and is used as a second part of the object stream, the event-related information including at least one of the following: an identifier of the at least one object, a type of the event, and metadata of the event.

Abstract: A method for monitoring a storage system, the method may include (a) generating a compute entity (CE) storage metric by each CE of a group of CEs to provide multiple CE storage metrics, wherein the multiple CE metrics are related to a monitoring period; and (b) calculating, during a calculation period, a group metric based on the multiple CE storage metrices; wherein the calculating includes performing multiple calculations iterations, wherein each calculation iteration includes (a) selecting an updating CE that belongs to the group of CEs and was not previously selected during the calculation period, (b) accessing, by the updating CE, a shared data structure that stores the group storage metric, and (c) updating the group storage metric using the CE storage metric of the updating CE.

Abstract: Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

Abstract: Methods and systems for a storage environment are provided, including generating a plurality of child (or tetris) write requests to write data for a write request using a plurality of subdivisions of a plurality of logical zones defined for a plurality of zoned solid state drives (ZNS SSDs) of a RAID array, each LZone mapped to one or more logical RAID zone (RZone) of the ZNS SSDs having a plurality of physical zones across a plurality of independent media units of each ZNS SSD; assigning a sequence number to each child (or tetris) write request corresponding to each subdivision, the sequence number indicating an order in which the child (or tetris) write requests are to be processed; and selecting, based on the assigned sequence number, one or more subdivisions for sequentially writing data to one or more RZones of the plurality of ZNS SSDs.