Abstract: A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor wafer and a fabrication method of semiconductor chips. According to the present invention, a semiconductor wafer containing a plurality of semiconductor chip portions has a plurality of chip scribe lanes formed between the semiconductor chip portions. A plurality of chip bonding pads are formed on the semiconductor chip portions of the wafer, and a plurality of wafer probing pads are formed on the chip scribe lanes. The wafer probing pads are electrically connected to internal circuits of the semiconductor chip portions and/or to corresponding ones of the chip bonding pads.

Abstract: A method of making an integrated circuit package for EPROM, CCD, and other optical integrated circuit devices is disclosed. First, a substrate base having metallized vias extending there through is provided. Second, an integrated circuit die is affixed to a first surface of the substrate, and is electrically connected to the metallized vias. Third, a bead of a viscous adhesive material is applied onto the substrate around the device. The bead covers the side surfaces of the device, the periphery of the upper first surface of the device, and the bond wires. The bead and the upper first surface of the die form a cavity above the die. Fourth, a layer of a transparent encapsulating material is deposited onto the die, within the cavity formed by the bead. Fifth, the encapsulating material is hardened, and subsequently forms an exterior surface of the package. The transparent encapsulating material allows light to illuminate the light sensitive circuitry of the device.

Abstract: A semiconductor substrate and a stackable semiconductor package and a fabrication method thereof which make it possible to form a highly-integrated semiconductor module within a limited area. The semiconductor substrate includes a non-conductive substrate main body having a plurality of patterned conductive wires formed therein, a cavity formed in an upper center portion of the substrate main body, and a plurality of via holes which perpendicularly pass through edge portions of the substrate main body. A stackable semiconductor package includes the above-described semiconductor substrate, having a semiconductor device positioned in its cavity with a molding compound, the semiconductor device being electrically connected to the conductive wires formed in the semiconductor substrate. Plural stackable semiconductor packages may be stacked such that the via holes are aligned, and a conductive material such as solder can be placed in the via holes to ensure electrical connection.

Abstract: A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

Abstract: A semiconductor device mount structure containing a semiconductor device (10), a connection substrate (30) disposed at the lower side of the semiconductor device (10), and leads (20) which are connected to external connection terminals (12) of the semiconductor device (10) at one ends thereof, turned back and connected to wires provided on the connection substrate (30) at the other ends thereof. The connection substrate (30) is constructed by plural carrier substrates. Each of the plural carrier substrates is right-angled isosceles triangular, and the plural carrier substrates are arranged so as to form a substantially square shape at the lower portion of the semiconductor device (10).

Abstract: A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure.

Abstract: A method for manufacturing chip stacks in which wafers are stacked one on top of the other. The wafer is provided with an adhesive foil on its bottom, and is subsequently cut into chips so that the adhesive foil remains intact and the chips adhering to the adhesive foil are stacked one on top of the other. A first layer of chips is reversibly attached to a baseplate, the adhesive foil is removed, the next layer of chips is attached to the bottom side of the chips already fastened to the baseplate, the adhesive foil is removed, and the last two steps are repeated until the desired number of chips is stacked one on top of the other.

Abstract: Semiconductor devices having bonding wires are encapsulated in a fluid molding resin, and the flow front of the molding resin can displace the bonding wires and create a short of the device. A semiconductor IC device is provided with dummy bonding wires to prevent or reduce the wire displacement by blocking the remaining bonding wires from direct exposure to the molding resin flow front in the mold cavity. Wire displacement or sweep of the dummy bonding wires causes the dummy bonding wires to contact their adjacent remaining bonding wires, but this contact does not cause a short in the device. The size of the semiconductor IC device is thereby reduced by increasing the allowable length of the bonding wires in the device, resulting in improved yields and lower production costs.

Abstract: An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure.

Abstract: Disclosed is a method for manufacturing a BiCMOS in which a complementary MOS transistor and a bipolar transistor are formed on the same substrate, comprising the steps of: providing a semiconductor substrate with impurities of a first conductivity type; forming field oxides for device isolation at the substrate to define a first group active region having two active regions and a second group active region having five active regions in series arrangement; forming a first mask pattern to expose three central active regions of the second group active region; forming a buried layer of a second conductivity type at a first depth from surfaces of the three central active regions using the first mask pattern; forming a second mask pattern to expose either one active region of the first group active region and two active regions at both edge portions of the second group active region; forming first well regions of the second conductivity type in which the impurities of the second conductivity type are distributed t

Abstract: Reverse short-channel effect is suppressed in a field effect transistor with a gate having a short length. The field effect transistor comprises a p-type silicon substrate, a gate electrode, paired lightly doped source/drain regions, and paired heavily doped source/drain regions. A boron concentration peak region is formed in the silicon substrate. A boron concentration peak region positioned at an end of the gate electrode has a length d of one fourth of a length L of the gate electrode, and extends from the end to the center of the gate electrode.

Abstract: Methods of forming electrical interconnects on semiconductor substrates include the steps of forming a first electrically insulating layer (e.g., silicon dioxide) and then forming a contact hole in the insulating layer to expose a layer underlying the insulating layer. A first electrically conductive region (e.g., W, Ti, Tin, Al) is then formed in the contact hole. A step is then performed to remove a portion of the first electrically insulating layer to define a recess therein which preferably surrounds an upper portion of the first conductive region. A second electrically conductive region (e.g., Al, Cu, W, Ti, Ta and Co) is then formed in the recess. Here, the first conductive region is preferably chosen to have good step coverage capability to fully bury the contact hole and the second conductive region is preferably chosen to have very low resistance even if some degree of step coverage capability is sacrificed. Planarization steps (e.