Abstract: The semiconductor memory of this invention includes a memory cell, a control word line selector/deriver circuit, a well driver circuit, a source line selector/deriver circuit, a pulse generation circuit for outputting a pulse signal in injecting electrons into a floating gate of the memory cell, a first delay circuit, a second delay circuit and a third delay circuit. The control word line selector/deriver circuit changes the potential of a control word line in response to a first delay signal received from the first delay circuit, the well driver circuit changes the potential of a well in response to a second delay signal received from the second delay circuit, and the source line selector/deriver circuit changes the potential of a source line in response to a third delay signal received from the third delay circuit.

Abstract: A voltage supply circuit has a resistive element, a p-channel MOS transistor, and n-channel MOS transistors. The resistive element and the p-channel MOS transistor are connected in parallel between a power source node and a node. The n-channel MOS transistors are connected in series between the node and the ground node. The voltage supply circuit supplies a threshold voltage of the n-channel MOS transistor to the node connected to a cell Vcc line of a memory cell in response to a test mode signal TE of the H level, and supplies an external source voltage in response to a test mode signal of the L level. In such a manner, a memory cell having an abnormal current in a standby mode can be detected by an operation test.