Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

Abstract: The present disclosure relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The disclosure also relates to the wafer that is produced by the new method.

Abstract: A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.

Abstract: To provide a display device with low power consumption. The display device includes a plurality of pixels each having a light-emitting element having a structure in which light emitted from a light-emitting layer is resonated between a reflective electrode and a light-transmitting electrode, wherein no color filter layers are provided or color filter layers with high transmittance are provided in pixels for light with relatively short wavelengths (e.g., pixels for blue and/or green), and a color filter layer is selectively provided in pixels for light with a long wavelength (e.g., pixels for red), and thereby maintaining color reproducibility and consuming less power.

Abstract: A method of manufacturing an organic light emitting display device includes defining pixels on a substrate, each of the pixels including a first area in which light is emitted in a first direction and a second area in which light is emitted in a second direction opposite the first direction; forming first electrodes respectively disposed in the first area of each of the pixels; forming a sacrificial layer in the first area and the second area of each pixel to cover the first electrodes; forming openings in the sacrificial layer to open a patterning area in the respective second area of each of the pixels; forming a conductive layer on the patterning areas and the sacrificial layer; removing the sacrificial layer; forming an intermediate layer including an organic emitting layer; and forming a third electrode on the intermediate layer.

Abstract: Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.

Abstract: A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source.

Abstract: There is provided a light emitting device including a plurality of nanoscale light emitting structures spaced apart from one another on a first conductivity-type semiconductor base layer, the plurality of nanoscale light emitting structures each including a first conductivity-type semiconductor core, an active layer and a second conductivity-type semiconductor layer, and an electrode connected to the second conductivity-type semiconductor layer. The electrode is disposed between a first nanoscale light emitting structure and a second nanoscale light emitting structure among the plurality of nanoscale light emitting structures, and the electrode has a height lower than a height of the plurality of nanoscale light emitting structures.

Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.

Abstract: An organic light-emitting display device which is transparent by improving a transmittance in transmitting regions and which reduces a voltage drop in an opposite electrode comprises: a substrate having a transmitting region and pixel regions separated from each other by the transmitting region; thin film transistors positioned on the substrate and disposed in the pixel regions, respectively; a passivation layer covering the thin film transistors, formed in the transmitting region and the pixel regions, and having a first opening formed in a location corresponding to at least a portion of the transmitting region; pixel electrodes formed on the passivation layer so as to be electrically connected to the thin film transistors, respectively, located in the pixel regions, and disposed so as to overlap and cover the thin film transistors, respectively; an opposite electrode facing the pixel electrodes, formed so as to be able to transmit light, and located in the transmitting region and the pixel regions; an organ

Abstract: Disclosed herein is a method for manufacturing a light emitting diode (LED) module, the method including: disposing a circuit board at a molding space formed by an upper mold and a lower mold; adding a filling material to the molding space; hardening the filling material to form a molding cover covering at least a portion of an upper surface, a lower surface, and a side surface of the circuit board, the molding cover having an opening exposing the lower surface of the circuit board; removing the upper mold and the lower mold from the circuit board; and disposing an LED on the upper surface of the circuit board.

Abstract: In a semiconductor device, a vertical transistor comprises: a first diffusion region on a substrate; a channel region on the first diffusion region and extending in a vertical direction; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate.

Abstract: A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor.

Abstract: A lighting device having a novel structure for integration of a plurality of light-emitting elements, and a manufacturing method thereof are provided. In the lighting device, a plurality of light-emitting elements is electrically connected to each other through plugs (connecting members) and a connection wiring for integration. The connection wiring is provided on a counter substrate and the plugs are provided over an element substrate or for the counter substrate. Such a connection structure enables an appropriate electrical connection between the plurality of light-emitting elements in the lighting device.

Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Abstract: According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.

Abstract: In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.

Abstract: A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.

Abstract: An optoelectronic component including a connection carrier including an electrically insulating film at a top side of the connection carrier, an optoelectronic semiconductor chip at the top side of the connection carrier, a cutout in the electrically insulating film which encloses the optoelectronic semiconductor chip, and a potting body surrounding the optoelectronic semiconductor chip, wherein a bottom area of the cutout is formed at least regionally by the electrically insulating film, the potting body extends at least regionally as far as an outer edge of the cutout facing the optoelectronic semiconductor chip, and the cutout is at least regionally free of the potting body.

Abstract: A light-emitting device of an embodiment of the present application comprises a semiconductor layer sequence provided with a first main side, a second main side, and an active layer; a beveled trench formed in the semiconductor layer sequence, having a top end close to the second main side, a bottom end, and an inner sidewall connecting the top end and the bottom end. In the embodiment, the inner sidewall is an inclined surface. The light-emitting device further comprises a dielectric layer disposed on the inner sidewall of the beveled trench and the second main side; a first metal layer formed on the dielectric layer; a carrier substrate; and a first connection layer connecting the carrier substrate and the semiconductor layer sequence.