Patents Examined by Ming-Loan T Tran
  • Patent number: 7671382
    Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: March 2, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shingo Sudo, Tatsuo Ota, Nobutake Taniguchi, Hiroshi Yoshida, Hironori Kashimoto
  • Patent number: 7592657
    Abstract: According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 11, a crystalline conductive film 21, a first conductive film 23, a ferroelectric film 24 and a second conductive film 25 on a silicon substrate 1 in sequence, forming a conductive cover film 18 on the second conductive film 25, forming a hard mask 26a on the conductive cover film 18, forming a capacitor upon etching the conductive cover film 18, the second conductive film 25, the ferroelectric film 24 and the first conductive film 23 using the hard mask 26a as an etching mask in areas exposed from the hard mask 26a, and etching the hard mask 26a and the crystalline conductive film 21 exposed from the lower electrode 23a using an etching condition under which the hard mask 26a is etched.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: September 22, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Wensheng Wang