Abstract: There is provided a semiconductor testing apparatus comprising a current measuring portion which converts a load current quantity at the time of application of a relatively high test voltage to a DUT to fall within a low-voltage range, and then subjects the low-voltage range to quantization conversion with a predetermined measurement resolution even when the relatively high test voltage is applied to the DUT.

Abstract: A probe card is vertically mounted generally perpendicular to a wafer undergoing life tests in a heated environment to limit exposure of the probe card to heat from the wafer chuck. The probe card and probe head assembly are mounted on a support rail which has one or more channels for the flow of cool air to a probe head assembly and the probe card, while it shields the flex cable from the hot chuck. The cool air flow disrupts convective hot air flow upwards from the heated chuck to the probe card and probe head and facilitates cooling of the probe card and probe head.

Abstract: A test fixture for testing a circuit board, comprising a top plate defining a board-bearing surface for receiving the circuit board to be tested thereon. The test fixture comprises a lid having a lid frame defining a peripheral rim, and a lid diaphragm movably mounted to the frame opposite the peripheral rim; the lid diaphragm defines an inner surface to which is mounted a circuit board securing member. The lid is movable between a first position where the frame rim engages the top plate to define a test chamber about the board-bearing surface and between the top plate, the frame and the diaphragm, and a second position where the lid is moved away from the top plate to allow access to the test chamber.

Abstract: A chip carrier for testing electrical performance of a passive component includes: a core layer having a plurality of conductive traces on a surface thereof; at least one first trace connected with the passive component and having a first predetermined position and two ends, wherein the two ends are respectively electrically connected to a first bond finger on the surface of the chip carrier and to a first ball pad on an opposite surface of the chip carrier; at least one second trace not connected with the passive component and having two ends and a second predetermined position located on the same surface as the first predetermined position, one end of the second trace being electrically connected to a second ball pad located on the same surface as the first ball pad; and a solder mask layer applied over the conductive traces, with the first and second predetermined positions exposed.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: A system of simulating resistive loads adapted for testing working characteristics of power supplies includes a power supply (100), a linking apparatus (10) and a resistance loading apparatus (40). The power supply has a plurality of outputs (120). The linking apparatus is electrically connected to the outputs of the power supply. The resistive load apparatus is electrically connected to the linking apparatus. The resistive load apparatus includes a plurality of resistance matching selectors.

Abstract: A power semiconductor module has a detector for detecting main circuit current passing through a power semiconductor element. The detector includes first and second circuit patterns; a bonding wire connected at first and second bonding points with the first and second circuit patterns, respectively; and a pair of terminal patterns extended from near the first and second bonding points of the first and second circuit patterns. The detector is designed to detect a potential difference between the pair of terminal patterns generated by flowing main circuit current through the first circuit pattern, the bonding wire and then the second circuit pattern, in order to detect a potential difference across the bonding wire.

Abstract: In-situ probing of closely spaced signals of SMT components uses a ribbon of flexible printed circuit material. Upon a first distal end of the ribbon are permanently soldered pins to be soldered to component leads carrying the desired signals. The ribbon may be bent to lie against a surface parallel to the plane of the PCB, where a small amount of adhesive or tape may secure it. That parallel surface may be an empty region of the PCB, may be the top of a component having peripheral leads that are being probed or the top of a nearby component, or (for signals emerging from beneath a BGA without peripheral leads) the parallel surface may be the top of the BGA part itself while the probe tips are soldered to the pins of a nearby SMT device, such as an R-Pack. A stiffener may be permanently carried by the ribbon proximate a location where it contacts the parallel surface. A second distal end couples the signal traces to small coaxial cables leading to the test equipment in use.

Abstract: A channel architecture for use in automatic test equipment is disclosed. The channel architecture comprises pattern generation circuitry and timing circuitry responsive to the pattern generation circuitry to generate timing signals. Formatting circuitry coupled to the output of the timing circuitry generates pulse waveforms for application to pin electronics circuitry. The pin electronics circuitry is responsive to the formatting circuitry for interfacing the automatic test equipment to a device-under-test. The pattern generation circuitry, the timing circuitry, the formatting circuitry and the pin electronics circuitry are formed on the same integrated circuit.

Abstract: A test key for bridging and continuity testing is provided, comprising at least one test unit, which is composed of a first strand and a second strand embedded or non-touching intertwined with each other. The strand comprising a closed hook, a corresponding extension and a corresponding connection. The corresponding connections are electrically connected to an external voltage by at least one test pad, wherein the closed hook of the first strand is parallel with the closed hook of the second strand. A first corner is formed between the closed hooks and the corresponding extension, causing the closed hook of the first strands to be adjacent and parallel with the closed hook and the extension of the second strand. Moreover, another corner is formed between the extension and the corresponding connection, causing the connection of the first strand to be adjacent and parallel with the extension of second strand, forming an intertwining pattern.