Abstract: A plurality of data devices are interfaced to a microprocessor using a serial data transfer mechanism. The parallel data from the data devices is serialized. The serial data streams are multiplexed via a data multiplexer. An index signal identifies the data device from which the serial data is received/transmit. When a receive buffer is at a predefined level of emptiness, a bit associated with that buffer is asserted. Likewise, when a transmit buffer is at a predefined level of emptiness, a bit within the index register associated with the transmit buffer is asserted. The assertion of a bit within the index register generates an interrupt. A CPU core receives the interrupt signal and reads the index register to determine which buffers need servicing. The CPU core deasserts one bit of the index register, which indicates the CPU core is going to service the buffer associated with that bit.

Abstract: Chipset or core logic for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (e.g., the memory bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Abstract: A method for queuing hardware control blocks for a system including a host microprocessor and a plurality of devices that each includes an onboard sequencer is based on a single host endless new hardware control block queue in a host memory that is managed such that the host endless new hardware control block queue never goes empty. Each device, that is coupled to the host microprocessor by an I/O bus, also has a device endless new hardware control block queue in a common hardware control block array. These device endless new hardware control block queues are managed such that the queues never are empty. A single device on the bus fetches hardware control blocks from the host endless hardware control block queue and loads the hardware control blocks in the common hardware control block array. The other devices on the I/O bus do not participate in the transfer of hardware control blocks to the common hardware control block array.

Abstract: An arrangement and a method respectively for handling or getting access to a digital buffer in a digital buffer memory where to each digital buffer a set of pointers is arranged in a reference memory. The arrangement includes a register arrangement defining the position of a digital buffer in the digital buffer memory, an offset value, an address calculation arrangement and an operating address register. For each of the pointers in a set relating to a digital buffer, a separate pointer register is provided and address data is input and stored substantially at the same time in each pointer register corresponding to a set of pointers. The subsequent address for reading/writing in the digital buffer memory is calculated and stored in at least the operating address register.

Abstract: Higher speed data transactions between a host computer's system memory and a plurality of slow peripheral devices are accomplished by providing distributed DMA functions along with distributed pre-fetch buffers. The first I/O device accesses the host bus via a first DMA channel and a first pre-fetch buffer, the second I/O device accesses the host bus via a second DMA channel and a second pre-fetch buffer, and the third I/O device accesses the host bus via a third DMA channel and a third pre-fetch buffer. In a first DMA transaction, the first pre-fetch buffer is filled with data being transferred between the first I/O device and the host system memory. While the data are transferred between the pre-fetch buffer and either the first I/O device or the system memory, the second pre-fetch buffer is being filled pursuant to a second DMA transaction between the second I/O device and the system memory.

Abstract: A method of actively guiding and helping the user is disclosed, in which various supporting functions can be performed in accordance with a particular user situation. The method is equipped with user situation detection data having at least a user situation and a corresponding interaction pattern activated in such a user situation, supporting function select data having at least a user situation and a corresponding user supporting function name to be activated in the particular user situation, and at least one user supporting function. Each time an input is received from the user, the contents of the input are stored as an operation log data. The interaction pattern data of the user situation detection data is compared with the operation log data.

Abstract: A data processing unit capable of solving a conventional problem in that a CPU cannot acquire the right of using a bus as long as a DMAC (Direct Memory Access Controller) has that right, and hence the operating ratio of the CPU reduces. A CPU bus is kept disconnected from the DMAC bus as long as the CPU disables the access request to a memory connected to the DMAC bus, and is connected to a DMAC bus in response to the access request unless the DMAC has the right of using a DMAC bus.

Abstract: An automatic volume block resizer for automatically resizing a volume in a disk drive system. The original volume includes original volume blocks each having an original volume block size, and the resized volume including new volume blocks each having a new volume block size. The volume block resizer comprises means for automatically aligning files contiguously on new volume block boundaries and means for redefining the volume for use with the new volume block size. The file aligning means comprises means for moving original volume blocks to available locations on the volume to create disk space equivalent to the new volume block size and to store the files on the new volume block boundaries. The files are stored contiguously; that is, they are defragmented as they are realigned onto the new volume block boundaries. The realignment is performed through the manipulation of original volume blocks of data.

Abstract: A method for dynamic reconfiguration of a message-passing interface from a Push model to a Pull model is disclosed. In the Push model, a host computer device moves data stored in a host local memory to an I/O peripheral shared memory, whereas in the Pull model, the I/O peripheral moves data from the host's shared memory to a local memory of the I/O peripheral. To dynamically reconfigure the message passing interface from the Push to the Pull model, the hosts waits for the I/O peripheral to cycle through power-on/reset, locates the I/O peripheral's inbound and outbound queues in memory, directs the I/O peripheral to clear its outbound queue of messages from previous inbound messages and initializes the allocated message frames as free messages. The host then posts a message to the I/O peripheral inbound queue instructing the I/O peripheral to initialize in the Pull model. The I/O peripheral then posts any messages currently being processed to the I/O peripheral outbound queue.

Abstract: A data capture system includes a data early latch, a data on-time latch, and a data late latch each coupled to receive an input data signal and a first, second, and third data strobe signal, respectively. When the respective data strobe signal is triggered the respective data latch captures, or latches, the input data signal at three intervals resulting in oversampled input data signals. The on-time data latch generates the latched data signal. The latched data signal is compared with the data early signal latched by the data early latch as well the data late signal latched by the data late latch. If the latched data signal and the data early signal are not equal, a delay controller increases the delays of the data strobe signals. If the latched data signal and the data late signal are not equal, the delay controller decreases the delays of the data strobe signals.

Abstract: I/O systems of computers typically utilize multiple layered drivers to process I/O requests. I/O requests are passed from one driver to another in a defined sequence with each driver performing its processing in turn. The present invention provides a system and method for interrupting the normal sequence of processing and for allowing drivers that would not normally process an I/O request to intervene and assume control for processing the I/O request. The system and method provides a flexible and extensible way to define special types of files or directories that require special processing by a particular driver. The present invention adds a "reparse point" attribute to a file or directory. The reparse point attribute preferably contains a tag which identifies a particular driver as the owner of the reparse point and a data value which can be used by the owner driver to store any information necessary or useful in processing an I/O request.

Abstract: A data transfer apparatus for DMA-transferring stream data between a memory and each of n ports.

Abstract: A multi-function peripheral device, connected to an information processing device, has a plurality of functional units for exerting mutually different functions by exchanging data with the information processing device. The multi-function peripheral device includes a specific command judgment unit for judging whether data from the information processing device contains a specific command corresponding to any one of the plurality of the functional units and a data supplier for acting when the specific command detector determines that the specific command exists. The data supplier thereupon supplies the data from the information processing device, including the specific command, to the one of the functional units to which the specific command corresponds.