Abstract: A shift circuit of a shift register includes an output terminal, an input terminal, a reset terminal. A voltage is applied to a first wiring in response to the output signal from the preceding stage shift circuit to the input terminal and in accordance with the predetermined voltage to the first wiring, outputting an externally applied signal to the output terminal. A voltage level of the first wiring is reduced in response to the output signal to the reset terminal by the preceding stage shift circuit. The voltage is applied to the second wiring in response to a change in the level of the voltage applied to the first wiring. The voltage is applied to a second wiring in response to the output signal to the reset terminal by the preceding stage shift circuit. A voltage level of the output signal is reduced in response to the predetermined voltage to the second wiring.

Abstract: A circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.