Abstract: A method of searching digital communication signals in a system includes combining a plurality of channel measurements, providing output of the combining of channel measurements as an added input to the plurality of channel measurements, and acquiring a signal symbol based on results from the combining of channel measurements without addressing all timing hypothesis individually via a correlation operation.
Type:
Grant
Filed:
July 2, 2003
Date of Patent:
April 20, 2010
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Robert W. Boesel, Theodore J. Myers, Tien Q. Nguyen
Abstract: An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to generate a first control signal in response to the demodulated signal. The third circuit may be configured to generate a second control signal in response to (i) the first control signal and (ii) a compensation signal. The fourth circuit may be configured to generate the seed value in response to the second control signal.
Abstract: A method of detecting the power loadings at a receiver wherein estimation of power loadings based on the received reference signals is unnecessary. Channel condition is obtained for each channel and transmission power loading per channel is detected according to channel condition, wherein estimation of power loadings based on the received reference signals is unnecessary. A received encoded information bit stream is then decoded according to the detected power loading per channel.
Abstract: A concatenated coding scheme, using an outer coder, interleaver, and the inner coder inherent in an FQPSK signal to form a coded FQPSK signal. The inner coder is modified to enable interative decoding of the outer code.
Abstract: A system, apparatus, method and article to converge a communications system receiver are described. The apparatus may include an interference canceller to receive an interference signal and to produce an adaptive signal. The interference canceller is adapted by a first adaptation module. An equalizer is coupled to the interference canceller. The interference canceller is located before the equalizer. The equalizer receives an input signal formed of a sum of a received input signal and the adaptive signal. A slicer is coupled to the equalizer and to the interference canceller. The slicer receives an equalized version of equalizer coefficients and produces a slicer error. The first adaptation module adapts the interference canceller utilizing a convolution of the interference signal with the equalizer coefficients, and multiplying the results by the slicer error. Other embodiments are described and claimed.
Abstract: A method and system for transmitting signals between communication nodes is presented. The method includes generating a first waveform that includes a shaped portion; generating a second waveform that includes a shaped portion; and combining the first and second waveforms including overlapping the shaped portion of the first waveform with the shaped portion of the second waveform and adding the overlapped portions of the waveforms. The method includes generating a signal including the combined first and second waveforms. At least one of the first and second waveforms includes a characteristic signature configured for synchronizing with the signal.
Type:
Grant
Filed:
February 3, 2006
Date of Patent:
March 30, 2010
Assignee:
Intellon Corporation
Inventors:
Lawrence W. Yonge, III, Timothy J. VanderMey
Abstract: An integrated circuit device for use in a node of a communication system is provided. The integrated circuit device includes a memory configured to store data written thereto by a receiver associated with the node in accordance with a receiver clock, and to read data therefrom by a transmitter associated with the node in accordance with a transmitter clock. The integrated circuit device also includes a control logic circuit that is in communication with the memory, and is configured to send a control signal to the transmitter to adjust a speed of the transmitter clock responsive to an operating condition of the memory.
Type:
Grant
Filed:
March 24, 2005
Date of Patent:
March 30, 2010
Assignee:
Agere Systems Inc.
Inventors:
Yasser Ahmed, Robert D. Brink, Gregory W. Sheets, Lane A. Smith
Abstract: In accordance with the present invention, a method and apparatus for estimating the noise and interference over the transmission band for OFDM systems are provided. Noise variance and signal-to-noise ratio (SNR) are important parameters for adaptive orthogonal frequency division multiplexing (OFDM) systems since they serve as a standard measure of signal quality. Conventional algorithms assume that the noise statistics remain constant over the OFDM frequency band, and thereby average the instantaneous noise samples to get a single estimate. In reality, noise is often made up of white Gaussian noise along with correlated colored noise that affects the OFDM spectrum unevenly. Provided is an adaptive windowing technique to estimate the noise power that takes into account the variation of the noise statistics across the OFDM sub-carrier index as well as across OFDM symbols. The proposed method provides many local estimates, allowing tracking of the variation of the noise statistics in frequency and time.
Abstract: A data transmitting device for transmitting data on a channel within a CDMA system may simultaneously convey data with a plurality of other data transmitting devices on one channel. The data transmitting device includes an interleaver that receives an interleaver pattern parameter, generates a respective interleaver pattern in accordance with the received parameter, and interleaves a source data stream using the generated interleaver pattern to produce an interleaved data stream. The generated interleaver pattern has interleaver characteristics that differ from the interleaver characteristics of at least one other data transmitting device that simultaneously transmits data on the channel.
Type:
Grant
Filed:
September 30, 2002
Date of Patent:
March 30, 2010
Assignee:
Panasonic Corporation
Inventors:
Christian Wengerter, Alexander Golitschek Edler Von Elbwart, Eiko Seidel
Abstract: An efficient architecture for a rake combiner is disclosed, for constructively combining the desired multi-path signals from a Code-Division Multiple-Access (CDMA) based system, such as a Third-Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) mode Wideband CDMA (W-CDMA) system, or an IS-95 CDMA system. The described rake combiner employs a single M-stage tap-delay line, an N+1 input adder, an arrangement of index offsets, pass gates, comparators and an M-stage counter to perform the combination, where M represents the delay spread in terms of symbol duration and N represents the number of rake fingers to be combined. The rake combiner architecture facilitates lowered resource requirements through use of a single tap-delay line in contrast to a conventional rake combiner which uses a series of M-stage tap-delay lines and an N input adder to perform the combination.
Type:
Grant
Filed:
April 3, 2003
Date of Patent:
March 23, 2010
Assignee:
STMicroelectronics Asia Pacific Pte. Ltd.
Inventors:
Christopher Anthony Aldrige, Ser Wah Oh
Abstract: A wired spread spectrum communication device, a method for communication thereof and a wired spread spectrum communication system capable of enabling easy establishment of synchronism are disclosed. In a transmitter unit of the wired spread spectrum communication device, a spreading code generator generates spread spectrum signals that are based on specified spreading codes, a strobe signal generator and a timing gate output the spread spectrum signals as sync signals at specified timings, and an adder superposes the sync signals to the spread information signals, while the adder further sends the information signals that have been superposed with the sync signals as transmitting signals to transmission paths.
Abstract: A bit/power loading method in an adaptive modulation-based multicarrier communication system computes ratios of modulation mode values to transmission power values sub-channel-by-sub-channel, selects a combination of sub-channels in which a sum of the ratios is maximized for a total number of bits to be simultaneously transmitted, and transmits signals in modulation modes corresponding to ratios of modulation mode values to transmission power values associated with the selected sub-channels. Because the bit/power loading method selects a combination of sub-channel modulation modes with the minimum total transmission power for a given number of bits on the basis of transmission power in each sub-channel modulation mode, the bits can be transmitted at the minimum transmission power in a given environment.
Type:
Grant
Filed:
March 24, 2005
Date of Patent:
March 16, 2010
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Pandharipande Ashish, Ho Yang, Hyoung-Woon Park, Ho-Jin Kim, Young-Ho Jung
Abstract: A data recovery apparatus and method for receiving at least an original clock and at least an original data stream output from a transmitter to output at least one recovery data are provided. The original data stream and the recovery data respectively include N steps in a period T of the original clock, wherein N is an integer larger than 0. The data recovery apparatus includes a sampling unit and a processing unit. The sampling unit samples the original data stream according to the original clock, wherein the sampling unit samples the corresponding data of the original data stream at least three times with T/(4N) sample period in each step. The processing unit receives and compares the sampled result output from the sampling unit, and recovers the sampled result to the recovery data according to the compared result.
Abstract: Generating a notch in an Orthogonal Frequency Division Multiplexing (OFDM) frequency spectrum includes determining a first active interference cancellation (AIC) tone, comparing the first AIC tone with an amplitude limit, in the event that the first AIC tone exceeds the amplitude limit, constraining the first AIC tone, and determining a second AIC tone based at least in part on the first AIC tone. An Active Interference Cancellation (AIC) tone generator includes an interface configured to receive a plurality of tones, a processing component coupled to the interface, configured to determine a first AIC tone, compare the first AIC tone with an amplitude limit, and in the event that the first AIC tone exceeds the amplitude limit, constrain the first AIC tone, and determine a second AIC tone based at least in part on the first AIC tone.
Abstract: A method for generating code sequences having good correlation properties comprising steps of selecting a code length comprising a number of chips, selecting a ruler which defines the position of non-zero values within the chips, and overlaying the non-zero values with an amplitude pattern.
Type:
Grant
Filed:
June 24, 2008
Date of Patent:
March 9, 2010
Assignee:
Alereon, Inc.
Inventors:
Vernon R. Brethour, Larry W. Fullerton, Marcus H. Pendergrass, James L. Richards
Abstract: In order to improve upon a degradation in performances due to inter-carrier interference without loss of transmission efficiency, antennas provided on a mobile body are made directional antennas. An antenna selection unit selects a directional antenna in such a manner that Doppler shift that is caused by movement of the mobile body will keep a constant sign that is positive or negative, a fading-variation calculation unit calculates the average value of fading variation on each path of a multipath environment, and a fading-variation compensation unit compensates the multipath fading variation based upon the average value.
Abstract: A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter.
Type:
Grant
Filed:
September 30, 2003
Date of Patent:
February 23, 2010
Assignee:
Rambus Inc.
Inventors:
Dennis Kim, Jason Wei, Yohan Frans, Todd Bystrom, Nhat Nguyen, Kevin Donnelly
Abstract: A method of jitter measurement is provided and includes sampling a device-under-test (DUT) output signal, having a repeating pattern, using an asynchronous clock over a desired period of time and mapping the samples onto a single period of the repeating pattern. Each period of the repeating pattern is sampled at least twice. A sampling frequency of the asynchronous clock is based on user inputs. Sampling the DUT signal comprises capturing logical state information representing each edge of a single period of the DUT signal at least once. The method further includes, separating the samples into subsets and mapping the sample subsets onto a single period of the repeating pattern wherein the samples within a particular subset are mapped to a set of times which are in the same order as in which the samples were obtained, processing the samples within each subset independently of samples in other subsets, and combining results of the processed subsets and processing the combined results of the subsets.
Abstract: A training sequence is created for space-time diversity arrangement, having any training sequence length, while limiting the training sequence to a standard constellation. Given a number of channel unknowns that need to be estimated, L, a training sequence can be creates that yields minimum means squared estimation error for lengths Nt=kNPRUS+L?1, for any positive integer k?1, where NPRUS a selected perfect roots-of-unity sequence (PRUS) of length N. The training sequence is created by concatenating k of the length N perfect roots-of-unity sequences, followed by L?1 initial symbols of that same PRUS. Good training sequences can be created for lengths Nt that cannot be obtained through the above method by concatenating a requisite number of symbols found through an exhaustive search.
Type:
Grant
Filed:
July 18, 2006
Date of Patent:
February 23, 2010
Inventors:
Naofal Al-Dhahir, Christine Fragouli, William Turin
Abstract: An improved method and apparatus for transmitting digital signals in a communications channel by compensating for distortions due to attenuation of high frequency components suffered by the digital signals. In a preferred embodiment, the digital signals are pulses and the compensation is performed at the transmitter without the need for an emphasis driver, by widening the pulses to compensate for the distortion in the channel that results in narrowing of the pulses incurred in the channel. The resulting pulse train is pre-compensated for the distortions caused by the communications channel. The amount of pre-compensation can be determined statically or dynamically.
Type:
Grant
Filed:
September 19, 2006
Date of Patent:
February 23, 2010
Assignee:
LSI Corporation
Inventors:
Mark J. Marlett, Mark Rutherford, Peter Windler