Patents Examined by Mohammad Karimy
  • Patent number: 8089070
    Abstract: An imager apparatus and associated starting material are provided. In one embodiment, an imager is provided including a silicon layer of a first conductivity type acting as a junction anode. Such silicon layer is adapted to convert light to photoelectrons. Also included is a semiconductor well of a second conductivity type formed in the silicon layer for acting as a junction cathode. Still yet, a barrier is formed adjacent to the semiconductor well. In another embodiment, a starting material is provided including a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Also included is a second silicon layer disposed adjacent to the oxide layer opposite the first silicon layer. Such second silicon layer is further equipped with an associated passivation layer and/or barrier.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: January 3, 2012
    Assignee: California Institute of Technology
    Inventor: Bedabrata Pain
  • Patent number: 8044457
    Abstract: In various embodiments, the invention relates to semiconductor structures, such as planar MOS structures, suitable as voltage clamp devices. Additional doped regions formed in the structures may improve over-voltage protection characteristics.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: October 25, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Javier Salcedo, Alan Righter
  • Patent number: 8039939
    Abstract: Provided are an embedded wiring board and a method of manufacturing the same. The embedded wiring board includes: a printed circuit board (PCB) including a first surface and a second surface, the first surface having a concave portion; through electrodes penetrating the PCB; a semiconductor device group embedded in the concave portion of the PCB, the semiconductor device group including bonding pads exposed in a direction of the first surface of the PCB; bumps disposed on the bonding pads, exposed in the direction of the first surface of the PCB; and a film substrate including a first surface and a second surface, the first surface including connection electrode patterns that are electrically connected to the bumps and the through electrodes, the film substrate having penetrated openings.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Taejoo Hwang
  • Patent number: 8022529
    Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masaya Kawano
  • Patent number: 7989884
    Abstract: A semiconductor structure includes a starting semiconductor substrate having a recessed portion. A semiconductor material is formed in the recessed portion, and has a higher resistivity than the starting semiconductor substrate. A body region extends in the semiconductor material, and has a conductivity type opposite that of the semiconductor material. Source regions extend in the body region, and have a conductivity type opposite that of the body region. A gate electrode extends adjacent to but is insulated from the body region. A first interconnect layer extends over and is in contact with a non-recessed portion of the starting semiconductor substrate. The first interconnect layer and the non-recessed portion provide a top-side electrical contact to portions of the starting semiconductor substrate underlying the semiconductor material.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: August 2, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chun-Tai Wu, Ihsiu Ho