Abstract: An insulated gate bipolar transistor and a preparation method thereof, and an electronic device. The insulated gate bipolar transistor includes: a drift region; an electrode structure on one side of the drift region; and an electric field stop layer arranged on one side of the drift region away from the electrode structure. The electric field stop layer includes a first sublayer and a second sublayer laminated together. The first sublayer is arranged close to the drift region. A junction depth of the first sublayer is greater than a junction depth of the second sublayer. A peak value of a doping concentration of the first sublayer is less than a peak value of a doping concentration of the second sublayer. A slope of a doping concentration curve of the first sublayer is less than a slope of a doping concentration curve of the second sublayer.

Abstract: In a method of manufacturing a semiconductor device, an alignment key is formed through a portion of a substrate including first and second surfaces opposite to each other, which is adjacent to the second surface of the substrate. A transistor including a gate structure and a source/drain layer is formed on the second surface of the substrate. A portion of the substrate adjacent to the first surface of the substrate is removed to expose the alignment key. A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate to be electrically connected to the source/drain layer. A power rail is formed on the first surface of the substrate to be electrically connected to the contact plug.

Abstract: A semiconductor device includes a semiconductor substrate, a cell region provided, and a termination region. The termination region surrounds the cell region and includes a plurality of first diffusion layers containing a first conductive impurity, a plurality of second diffusion layers each disposed on an outer side of each of the plurality of first diffusion layers and having a concentration of the first conductive impurity lower than that of the first diffusion layers, and a plurality of conductive layers opposing the first diffusion layers and the second diffusion layers on the front face of the semiconductor substrate, the plurality of conductive layers electrically connected to the first diffusion layers, the plurality of conductive layers each having an outer end portion. On a lower side of the outer end portion, any one of the plurality of second diffusion layers is present.

Abstract: The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof.

Abstract: Provided is an inorganic light emitting device including a first semiconductor layer, a second semiconductor layer, an active layer disposed between the first semiconductor layer and the second semiconductor layer, a first electrode covered to the first semiconductor layer, a second electrode covered to the second semiconductor layer, an insulating layer covered the first electrode and the second electrode, and including via holes at positions corresponding to the first electrode and the second electrode, and a first conductive member and a second conductive member coupled to the first electrode and the second electrode, respectively, through the via holes, wherein a distance between the first conductive member and the second conductive member is greater than a distance between the first electrode and the second electrode.

Abstract: Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.

Abstract: Provided is a semiconductor device including a semiconductor substrate. The semiconductor substrate has: an active portion; and a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction. The semiconductor device further includes: a gate runner provided between the active portion and an end side of the semiconductor substrate; and a plurality of gate polysilicon disposed apart from each other along the end side and respectively connecting the plurality of gate trench portions to the gate runner.

Abstract: A light receiving element array includes a substrate and a laminated semiconductor structure that is formed on the substrate. The laminated semiconductor structure includes a light absorbing layer that is disposed above the substrate and a plurality of window layers of a first conductivity type that are formed apart from each other on the light absorbing layer. Inside the laminated semiconductor structure, there is formed, for each window layer, a first of second conductivity type region that extends into the light absorbing layer from a surface of the window layer at an opposite side to the light absorbing layer. Inside the light absorbing layer, there is formed a second of second conductivity type region that is disposed such as to surround each of the plurality of window layers in plan view and extends from a surface of the light absorbing layer at an opposite side to the substrate toward a surface of the light absorbing layer at the substrate side.

Abstract: A semiconductor device including a semiconductor substrate, a parallel pn layer and a device structure provided in the semiconductor substrate, first and second electrodes respectively provided at two main surfaces of the semiconductor substrate, the first electrode being electrically connected to the device structure. The parallel pn layer includes first-conductivity-type column regions and second-conductivity-type column regions that are adjacently disposed and repeatedly alternate with one another in a first direction parallel to the first main surface, that each extend in a second direction parallel to the first main surface and orthogonal to the first direction, and that are of a same impurity concentration. A portion of the second-conductivity-type column regions is shorter than the rest thereof. The parallel pn layer has a first portion and a second portion respectively closer to the first and second main surfaces, the first portion being more p-rich, and less n-rich, than the second portion.

Abstract: conductivity type, a first region doped with the first conductivity type, a second region doped with the second conductivity type, N first oxide layers and K second oxide layers. The second region is located above the second drain region. The first region is located above the drain region and at a side of the second region. The source region is located above the first region and the second region. The first oxide layers are located at a side in the second region close to the source region. The second oxide layers are located at a side in the first region close to the drain region.

Abstract: Disclosed is a technique for improving performance of a semiconductor device having a trench gate type power MOSFET. Concretely, a method of manufacturing a semiconductor device having a trench gate type power MOSFET comprising: forming a trench in a semiconductor substrate; introducing both of a p-type impurity (Boron) and carbon (C) into a bottom surface of the trench to form a p-type impurity introduced region; forming a gate electrode to fill the trench; forming a channel forming region and a source region at the side of the trench in which the gate electrode is filled; and subjecting a heat treatment to the p-type impurity introduced region to form an electric field relaxation layer having suppressed crystal defects and a controlled shape.

Abstract: A semiconductor structure including a substrate, an epitaxy layer, an electrode structure, a first sidewall doping region, a second sidewall doping region, and a bottom doping region is provided. The substrate has a first conductivity type. The epitaxy layer has a first conductivity type and is disposed on the substrate. The electrode structure is disposed in the epitaxy layer. The electrode structure extends along a first direction. The first sidewall doping region has the first conductivity type and is disposed on one side of the electrode structure. The second sidewall doping region has a second conductivity type different than the first conductivity type and is disposed on the other side of the electrode structure. The bottom doping region has the second conductivity type and is disposed under the electrode structure. The second sidewall doping region is connected to the bottom doping region.

Abstract: The present disclosure is directed to techniques of fabricating hybrid transistors that combine both TFETs and MOSFETs. The techniques may be commonly integrated such that TFET regions are formed in the same fabrication stages used to fabricate CMOS regions. The TFET and MOSFET may be stacked vertically to reduce the footprint area of the hybrid transistor, which may lead to further semiconductor IC device scaling. The hybrid transistor may utilize a backside power distribution network (BSPDN). The utilization of the BSPDN may reduce resistances, which may result in performance increases. Further, the utilization of the BSPDN may further reduce the footprint area of the hybrid transistor, which may provide for continued scaling. Further, the utilization of the BSPDN may further reduce signal and power potential routing complexities.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, first to fourth semiconductor regions, a gate electrode, and a second electrode. The third semiconductor region is located on a portion of the second semiconductor region. The fourth semiconductor region includes a first portion positioned on the third semiconductor region and a second portion arranged with the first portion in a second direction. A first-conductivity-type impurity concentration of the first portion is less than a first-conductivity-type impurity concentration of the second portion. The gate electrode faces the second semiconductor region via a gate insulating layer in the second direction. The second electrode is located on the second and fourth semiconductor regions. The second electrode contacts the first and second portions. The second electrode includes a connection part that contacts the third semiconductor region and the portion of the second semiconductor region in the second direction.

Abstract: A semiconductor structure includes a semiconductor channel structure that has a body and a tip and a dielectric spacer adjacent to the tip. The tip is no less than 70% the thickness of the body.

Abstract: A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.

Abstract: A semiconductor device includes a semiconductor substrate having a drift layer of a first conductivity type and a collector layer of a second conductivity type. A first buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the drift layer and the collector layer and a second buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the first buffer layer and the collector layer. A kurtosis of a peak of an impurity concentration of the second buffer layer is lower than a kurtosis of a peak of an impurity concentration of the first buffer layer.

Abstract: The inventive concept provides a chip stack structure including a first semiconductor chip and a second semiconductor chip bonded to each other, and a semiconductor package including a plurality of chip stack structures stacked in a vertical direction.

Abstract: A semiconductor device according to the present embodiment includes: a first electrode; a first semiconductor region of a first conductivity type disposed above the first electrode; a second semiconductor region of a second conductivity type disposed on the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region; a second electrode disposed in the first semiconductor region; a third electrode facing the second semiconductor region via a second insulating film; a fourth electrode having a portion adjacent to a part of the second semiconductor region and the third semiconductor region in the second direction, the second semiconductor region, and the third semiconductor region; and a fifth electrode disposed in the first insulating film, having a bottom located closer to the first electrode than a bottom of the portion, having a top located on an upper surface of the first insulating film.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.