Abstract: A semiconductor structure includes a semiconductor channel structure that has a body and a tip and a dielectric spacer adjacent to the tip. The tip is no less than 70% the thickness of the body.

Abstract: A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.

Abstract: A semiconductor device includes a semiconductor substrate having a drift layer of a first conductivity type and a collector layer of a second conductivity type. A first buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the drift layer and the collector layer and a second buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the first buffer layer and the collector layer. A kurtosis of a peak of an impurity concentration of the second buffer layer is lower than a kurtosis of a peak of an impurity concentration of the first buffer layer.

Abstract: The inventive concept provides a chip stack structure including a first semiconductor chip and a second semiconductor chip bonded to each other, and a semiconductor package including a plurality of chip stack structures stacked in a vertical direction.

Abstract: A semiconductor device according to the present embodiment includes: a first electrode; a first semiconductor region of a first conductivity type disposed above the first electrode; a second semiconductor region of a second conductivity type disposed on the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region; a second electrode disposed in the first semiconductor region; a third electrode facing the second semiconductor region via a second insulating film; a fourth electrode having a portion adjacent to a part of the second semiconductor region and the third semiconductor region in the second direction, the second semiconductor region, and the third semiconductor region; and a fifth electrode disposed in the first insulating film, having a bottom located closer to the first electrode than a bottom of the portion, having a top located on an upper surface of the first insulating film.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor integrated circuit device may include a first region, a second region, a pad structure and an electrostatic discharge (ESD) connection. The first region may be positioned adjacent to a semiconductor substrate. An ESD protection circuit may be integrated in the first region. The second region may be stacked on the first region. A plurality of memory cells may be formed in the second region. The pad structure may be arranged over the second region to receive an external voltage. The ESD connection may include a plurality of lower conductive wirings in the first region. At least one of the lower conductive wirings may be electrically connected with the ESD protection circuit. The at least one of the lower conductive wirings may be drawn to a portion corresponding to the pad structure.

Abstract: A display device including a display panel including a base layer, a circuit layer disposed on the base layer, and a pad part having a plurality of pads disposed on the base layer; and a driving chip disposed on the pad part and including a plurality of chip pads. The plurality of pads include a first pad having a smaller area than a corresponding chip pad among the plurality of chip pads and a second pad electrically connected to the circuit layer.

Abstract: In a general aspect, a semiconductor device can include a semiconductor substrate, a trench formed in the semiconductor substrate and a first dielectric layer lining the trench. The semiconductor device can further include a first semiconductor material disposed in a lower portion of the trench. The first dielectric layer being can be disposed between the semiconductor substrate and the first semiconductor material. The semiconductor device can also include a second dielectric layer disposed on the first semiconductor material and a second semiconductor material disposed in an upper portion of the trench. The first dielectric layer can be disposed between the semiconductor substrate and the second semiconductor material. The second dielectric layer can be disposed between the first semiconductor material and the second semiconductor material. The semiconductor device can also include at least one of a diode or a resistor defined in the second semiconductor material.

Abstract: A display device includes a substrate on which a plurality of sub-pixels including at least one defective sub-pixel are defined; a light emitting element disposed in each of the sub-pixels; a driving transistor disposed in each of the sub-pixels and having a source electrode connected to a cathode of the light emitting element; a capacitor disposed in each of the sub-pixels and connected between a gate electrode and the source electrode of the driving transistor; and a reflector disposed in each of the sub-pixels and electrically connected to the cathode. In the defective sub-pixel, the gate electrode and the source electrode of the driving transistor are electrically connected through the capacitor. Accordingly, according to the present disclosure, the defective sub-pixel can be easily darkened or blackened by performing a welding process on a capacitor including a plurality of electrodes spaced apart from each other in the defective sub-pixel.

Abstract: A trench field effect transistor comprising a substrate. An epitaxial buffer layer is formed overlying the substrate. An epitaxial device layer is formed overlying the epitaxial buffer layer. A device body layer is formed overlying the epitaxial device layer. The substrate, epitaxial buffer layer, epitaxial device layer, and device body layer comprise silicon carbide. A trench formed in the device body layer into at least a portion of the epitaxial body layer. An insulating layer formed on the walls of the trench. A bottom of the trench is etched isotropically and forms a curved surface. The trench bottom after the isotropic etch extends past the walls of the trench and couples to the trench walls in a curve. An oxide layer is formed overlying the trench bottom and has a corresponding curve similar to the trench bottom. A gate oxide is formed on at least one wall of the trench.

Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

Abstract: The present disclosure relates to a semiconductor package that may include a package substrate with a first surface and an opposing second surface, a first device coupled to the first surface of the package substrate, a redistribution frame coupled to the second surface of the package substrate, a plurality of solder balls coupled to the second surface of the package substrate, a second device coupled to the redistribution frame, and a printed circuit board coupled to the plurality of solder balls on the second surface of substrate, wherein the redistribution frame coupled with the second device and the plurality of solder balls are positioned between the package substrate and the printed circuit board.

Abstract: A semiconductor device includes a semiconductor layer, a first conductive type first region formed in a surface layer portion of a first principal surface of the semiconductor layer, a cell structure having a second conductive type second region formed in a surface layer portion of the first region, a first conductive type third region formed in the surface layer portion of the first region such that third region is in contact with the second region, and a control electrode opposing the second region via a first insulating film adjacent to the second region, the control electrode forming a current path in the second region, a first electrode layer formed on the first principal surface such that the first electrode layer covers the cell structure, and electrically connected to the third region, a second electrode layer formed on the first principal surface separately from the first electrode layer.

Abstract: A display panel and a display apparatus are provided. The display panel includes a plurality of data lines each and a plurality of connecting lines that are located in a display area, and a plurality of pads located in a non-display area. Each of the plurality of data lines extends in a first direction. Each of the plurality of connecting lines has a first end connected with one of the plurality of data lines, and a second end connected with one of the plurality of pads. The display area includes a first boundary close to the pads. The connecting line includes a first segment extending from the first boundary into the display area in the first direction. At least one connecting line has a length D1 in the first direction, and the display area has a length D0 in the first direction. D1 is greater than D0/2.

Abstract: A semiconductor device cell includes a JFET region adjacent a channel region, the JFET region defining a periphery of the semiconductor device cell. The JFET region includes a first corner region and a second corner region separated by a JFET intermediate region. A first width of the JFET intermediate region extending from an edge of the JFET intermediate region abutting a periphery of the channel region to the periphery of the semiconductor device cell is greater than a second width of the JFET region extending from an edge of at least one of the first corner region and the second corner region abutting the periphery of the channel region to the semiconductor cell periphery.

Abstract: Provided is a semiconductor device including: a semiconductor substrate having a drift region of a first conductivity type; an active portion, in which at least one of a transistor portion and a diode portion is provided, in the semiconductor substrate; and an edge termination structure portion provided farther outward than the active portion in the semiconductor substrate, wherein the edge termination structure portion has a plurality of guard rings of a second conductivity type provided in contact with an upper surface of the semiconductor substrate, and an embedded dielectric film arranged between two guard rings and at least partially embedded in the semiconductor substrate, and the guard rings are provided up to a position below the embedded dielectric film.

Abstract: A trench gate type IGBT includes a plurality of trenches, including a plurality of gate trenches having a gate region inside, and a plurality of emitter trenches having an emitter region connected to an emitter electrode. A mesa section adjacent to the trench has a second mesa region, which does not function as a channel; and a contact, which connects the emitter electrode; the second mesa region being sandwiched between the gate trench and the emitter trench.

Abstract: A semiconductor device includes first and second electrodes, a semiconductor part, a structure body, and an insulating part. The semiconductor part includes first to fifth semiconductor regions. The structure body includes a gate part and a dummy part. The gate part includes at least one gate electrode. The dummy part includes at least two dummy electrodes. The gate part and the dummy part are alternately arranged. The insulating part is located between the gate electrode and the semiconductor part. The gate part is located in the fourth semiconductor region. A first potential is applied to the second electrode. A second potential that is greater than the first potential is applied to the gate electrode. A third potential that is greater than the first potential is applied to the dummy electrode located at a position next to the gate part.

Abstract: An image sensor includes a semiconductor substrate including a first surface and a second surface and having a photoelectric conversion region disposed therein. A floating diffusion region is disposed within the semiconductor substrate. The floating diffusion region is adjacent to the first surface. A buried gate structure is disposed within a buried gate trench extending from the first surface of the semiconductor substrate towards an interior of the semiconductor substrate, the buried gate structure including a first buried gate electrode inside a first buried gate trench adjacent to a first side part of the floating diffusion region, and a second buried gate electrode inside a second buried gate trench spaced apart from the first buried gate trench and adjacent to a second side part of the floating diffusion region, the second side part being opposite to the first side part.