Abstract: Provided is a semiconductor device including a semiconductor substrate. The semiconductor substrate has: an active portion; and a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction. The semiconductor device further includes: a gate runner provided between the active portion and an end side of the semiconductor substrate; and a plurality of gate polysilicon disposed apart from each other along the end side and respectively connecting the plurality of gate trench portions to the gate runner.

Abstract: One embodiment provides a power semiconductor device that includes a semiconductor body. A source region of a first conductivity type is disposed at a top side the semiconductor body. A channel region of a second conductivity type is disposed in the semiconductor body below the source region and a drift region of the first conductivity type is disposed in the semiconductor body below the channel region. A trench extends from the top side through the source region and through the channel region and ending in the drift region. As seen in a top view of the top side, the trench comprises a plurality of branch-offs. A gate electrode is disposed within the trench and a shield region of the second conductivity type is located at least partially below a branch-off of the trench.

Abstract: A method for forming a semiconductor structure is provided. The method includes: forming a trench in a semiconductor substrate; forming a gate lining layer along a lower portion of the trench; filling a gate electrode layer over the gate lining layer in the lower portion of the trench; forming a first sacrificial layer along a sidewall of an upper portion of the trench; forming a barrier layer along a sidewall of the first sacrificial layer and over a top surface of the gate electrode layer; removing a first portion of the barrier layer along the sidewall of the first sacrificial layer, thereby leaving a second portion of the barrier layer over the top surface of the gate electrode layer; forming a semiconductor layer over the second portion of the barrier layer; removing the first sacrificial layer; and forming a capping layer over the semiconductor layer.

Abstract: Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.

Abstract: A chip package includes a chip, a first support layer, a light emitter, a first light transmissive sheet, a redistribution layer, and a conductive structure. A top surface of the chip has a conductive pad and a first light receiver. The first support layer is located on the top surface of the chip. The light emitter is located on the top surface of the chip. The first light transmissive sheet is located on the first support layer and covers the first light receiver. The redistribution layer is electrically connected to the conductive pad and extends to a bottom surface of the chip. The conductive structure is located on the redistribution layer that is on the bottom surface of the chip.

Abstract: An assembly structure including a plurality of spacers, and a method of manufacturing the same are provided. The assembly structure includes a base material and a plurality of spacers disposed over the base material. Each of the plurality of spacers has a first lateral surface and a second lateral surface opposite to the first lateral surface. The second lateral surface is substantially parallel with the first lateral surface. A ratio of a height of the second lateral surface to a height of the first lateral surface is greater than 90%.

Abstract: A first VTFET is provided on a wafer. A second VTFET is adjacent to the first VTFET on the wafer. A backside power deliver network is on a backside of the wafer. A shared frontside contact is on a frontside of the wafer. The shared frontside contact is connected to a first top source/drain region of the first VTFET, a second top source/drain region of the second VTFET, and the backside power delivery network.

Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; a semiconductor layer provided between the first electrode and the second electrode, having a first face and a second face, and containing silicon; a first semiconductor region of n-type; a second semiconductor region of p-type disposed the first semiconductor region and the first face; a third semiconductor region of n-type between the second semiconductor region and the first face; a gate electrode facing the second semiconductor region; and a metal silicide layer between the first electrode and the second semiconductor region and between the first electrode and the third semiconductor region, including a top surface, a first bottom surface in contact with the third semiconductor region, and containing gold or a platinum group element. The n-type impurity concentration in the third semiconductor region monotonically decreases from the first bottom surface toward the second electrode.

Abstract: An microelectronic device includes a semiconductor substrate, at least one sensing element disposed in the semiconductor substrate, at least one multi-film stack disposed on the semiconductor substrate and covering the sensing element, a refill layer disposed on the semiconductor substrate and encircling the multi-film stack, and a spacer layer disposed on the multi-film stack and the refill layer. An area of a top surface of the multi-film stack is less than an area of a bottom surface of the multi-film stack. The multi-film stack has a first dimension measured in a direction, a section of the refill layer has a second dimension measured in the direction, and a ratio of the second dimension to the first dimension is in a range from 0.03 to 0.06. The refill layer and the spacer layer are organic layers.

Abstract: A power semiconductor device includes a semiconductor layer based on silicon carbide (SiC), a vertical drift region positioned to extend in a vertical direction inside the semiconductor layer and having a first conductive type, a well region positioned in at least one side of the vertical drift region to make contact with the vertical drift region and having a second conductive type, recess gate electrodes extending from a surface of the semiconductor layer into the semiconductor layer and buried in the vertical drift region and the well region to cross the vertical drift region and the well region in a first direction, source regions positioned in the well region between the recess gate electrodes and having the first conductive type, and insulating-layer protective regions surrounding lower portions of the recess gate electrodes, respectively, in the vertical drift region, and having the second conductive type.

Abstract: A display device is disclosed that includes a substrate, a light-emitting element disposed on the substrate, a first insulating layer disposed on the light-emitting element, and a driving element disposed on the first insulating layer, wherein the driving element passes through the first insulating layer and is electrically connected to the light-emitting element.

Abstract: A light emitting display apparatus includes a first base substrate including a first pad portion including a first pad connected to a routing line, a display area, and a first boundary region provided between the display area and the first pad portion and a second base substrate including a second pad portion including a second pad connected to the routing line, a connection region where a link line is provided, and a second boundary region provided between the connection region and the second pad portion. The second base substrate is bonded to a rear surface of the first base substrate, a thickness of the first base substrate in the first pad portion is less than a thickness of the first base substrate in the first boundary region, and a thickness of the second base substrate in the second pad portion is less than a thickness of the second base substrate in the second boundary region.

Abstract: An insulated gate bipolar transistor and a preparation method thereof, and an electronic device. The insulated gate bipolar transistor includes: a drift region; an electrode structure on one side of the drift region; and an electric field stop layer arranged on one side of the drift region away from the electrode structure. The electric field stop layer includes a first sublayer and a second sublayer laminated together. The first sublayer is arranged close to the drift region. A junction depth of the first sublayer is greater than a junction depth of the second sublayer. A peak value of a doping concentration of the first sublayer is less than a peak value of a doping concentration of the second sublayer. A slope of a doping concentration curve of the first sublayer is less than a slope of a doping concentration curve of the second sublayer.

Abstract: In a method of manufacturing a semiconductor device, an alignment key is formed through a portion of a substrate including first and second surfaces opposite to each other, which is adjacent to the second surface of the substrate. A transistor including a gate structure and a source/drain layer is formed on the second surface of the substrate. A portion of the substrate adjacent to the first surface of the substrate is removed to expose the alignment key. A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate to be electrically connected to the source/drain layer. A power rail is formed on the first surface of the substrate to be electrically connected to the contact plug.

Abstract: A semiconductor device includes a semiconductor substrate, a cell region provided, and a termination region. The termination region surrounds the cell region and includes a plurality of first diffusion layers containing a first conductive impurity, a plurality of second diffusion layers each disposed on an outer side of each of the plurality of first diffusion layers and having a concentration of the first conductive impurity lower than that of the first diffusion layers, and a plurality of conductive layers opposing the first diffusion layers and the second diffusion layers on the front face of the semiconductor substrate, the plurality of conductive layers electrically connected to the first diffusion layers, the plurality of conductive layers each having an outer end portion. On a lower side of the outer end portion, any one of the plurality of second diffusion layers is present.

Abstract: The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof.

Abstract: Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.

Abstract: Provided is an inorganic light emitting device including a first semiconductor layer, a second semiconductor layer, an active layer disposed between the first semiconductor layer and the second semiconductor layer, a first electrode covered to the first semiconductor layer, a second electrode covered to the second semiconductor layer, an insulating layer covered the first electrode and the second electrode, and including via holes at positions corresponding to the first electrode and the second electrode, and a first conductive member and a second conductive member coupled to the first electrode and the second electrode, respectively, through the via holes, wherein a distance between the first conductive member and the second conductive member is greater than a distance between the first electrode and the second electrode.

Abstract: Provided is a semiconductor device including a semiconductor substrate. The semiconductor substrate has: an active portion; and a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction. The semiconductor device further includes: a gate runner provided between the active portion and an end side of the semiconductor substrate; and a plurality of gate polysilicon disposed apart from each other along the end side and respectively connecting the plurality of gate trench portions to the gate runner.

Abstract: A light receiving element array includes a substrate and a laminated semiconductor structure that is formed on the substrate. The laminated semiconductor structure includes a light absorbing layer that is disposed above the substrate and a plurality of window layers of a first conductivity type that are formed apart from each other on the light absorbing layer. Inside the laminated semiconductor structure, there is formed, for each window layer, a first of second conductivity type region that extends into the light absorbing layer from a surface of the window layer at an opposite side to the light absorbing layer. Inside the light absorbing layer, there is formed a second of second conductivity type region that is disposed such as to surround each of the plurality of window layers in plan view and extends from a surface of the light absorbing layer at an opposite side to the substrate toward a surface of the light absorbing layer at the substrate side.