Abstract: A network interface device and a method of transferring data between a host and a network medium employs transmit descriptors that do not contain transmit status information. Upon fetching a transmit data frame from a host system memory at a location pointed to by a transmit descriptor, the network interface device immediately generates an interrupt to the CPU to allow the CPU to re-use the buffers in which the data frame was stored. At the same time, the network interface device attempts transmissions of the data frame to the network medium. Transmit status information is kept in statistics counters on the network interface device.

Abstract: The present invention provides an electronic switching device for a universal serial bus (USB) interface, which can connect several different electronic devices each having a universal serial bus (USB) interface when needed. By manually enabling a switch of the electronic switching device for a universal serial bus (USB) interface, a trigger signal generated from a trigger signal generator will be outputted to a control signal generator to generate a control signal for connecting related electronic devices. A delay signal generator can be added to avoid the intermediate devices being operated unintentionally.

Abstract: Computer system performance may be significantly enhanced by optimizing data throughput during input/output (I/O) operations. In turn, data throughput, during an I/O operation, may be optimized by adaptively modifying the I/O strategy at runtime, and/or continuously throughout the I/O operation, regardless of the specific hardware configuration associated with the I/O devices involved with the I/O operation, as well as additional factors that might otherwise impact the efficiency of the I/O operation.

Abstract: Data is converted from a first granularity to a second granularity different from the first granularity. The ratio “n” of the second granularity of the data to the first granularity of the data is determined as a power of 2. The least significant n bits of the beginning alignment of the data are added to the least significant n bits of the beginning count of the data, and the carry bit of the sum is designated as “c”. A logical “OR” is performed of the bits of the resulting sum to obtain a value designated as “d”. A number of data units, equal to the sum of “c” and “d”, is added to the data.

Abstract: The invention provides apparatus for the transfer of data/command between a master controller and one or more client controllers. The apparatus in accordance with the invention includes a bi-directional data bus for conveying plural bits of data or command between a master controller and one or more client controllers; direction signal controlling the direction in which data or command bits are conveyed on the data bus as between the master controller and a connected one of the one or more client controllers; a pair of ready signals including a transmit ready signal asserted by a source of data or command bits placed on the data bus and including a receive ready signal asserted by a destination for the data or command bits placed on the data bus; and a clock signal for indicating the presence of valid data or command bits on the data bus on a leading or trailing edge thereof. Preferably, a command/data signal is also provided to indicate the type of information placed on the data bus by the source.

Abstract: An input/output circuit in which a reset control circuit is provided in an NC board, and a logic circuit comprising a REG0 register and a REG1 register each for setting an object for reboot processing, two inverters, an AND gate, and an OR gate is provided in the reset control circuit. According to the setting in the registers, a reset signal RST* for starting reboot processing to the NC board while a PC control section is kept on operating is validated by the logic circuit. On the other hand the reset signal RST* is invalidated by the logic circuit when the reboot processing is executed to the PC control section.

Abstract: A keyboard is programmatically adapted to enable an application in a run time environment to distinguish operator keys (ALT/CTRL), not otherwise recognizable on a standard keyboard and special keys not otherwise recognizable on a non-standard keyboard by the application, when actuated. In one embodiment, a native Dynamic Link Library (DLL) is created in memory to capture the keystroke stream and maintain state information about the keyboard. A Java Native Interface (JNI) is created in the DLL and provided to a Java application. At initialization time, the Java application loads the native DLL with extended program instructions relating to key recognition in its static constructor. The Java application receives notification when an ALT or CTRL key is actuated. At that time the Java application calls the native DLL to receive the extended program instruction to determine whether the right or left ALT or CTRL key was actuated.

Abstract: A stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the steps of: 1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device; 2) receiving a signal in the controller from the I/O device at any time during the sending step, to terminate the transmission burst; 3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent; 4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and, 5) repeating the above steps until the stream of data is received in its entirety by the I/O device.

Abstract: A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the input queue (12). The input queue (12) queues commands and requests a number of output queue credits in response to receiving a command. The input queue (12) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue (14) queues commands and requests a number of output queue credits in response to receiving a command.

Abstract: A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

Abstract: A command queue control device, when there is the command which is not completed in spite of a lapse of prescribed time period, is capable of facilitating the command processing of the disk device, even though delay occurs in the command processing of the disk device, by causing the disk device to facilitate acceleration of the command.

Abstract: A system for interconnecting a plurality of interdependent fiber channel loops or fabrics. The system preferably comprises a first server which includes a PCI bus and a fibre channel to PCI bus adapter for each one of the plurality of the independent fibre channels. Each fibre channel to PCI bus adapter is configured to connect one of the plurality fibre channels to the PCI bus at the first server. The plurality of independent fibre channels then communicate with each other across the PCI bus of the first server utilizing the intelligent I/O (I2O) routing of the fibre channel to PCI bus adapters. The plurality of fibre channels are configured to communicate with the other fibre channels, as well as the first server via the PCI bus. This system can be configured such that any one of the plurality of fibre channels can include one or more devices connected thereto in addition to the first server.

Abstract: A method of simple network synchronization in a bus extension system with expanded capabilities wherein a plurality of independently-operable multimedia multiplexing devices are connected to the same network in parallel. The method of network synchronization for multiplexing devices connected by parallel through an extension bus is provided wherein one of two or more multiplexing devices is used as a clock master and other remaining multiplexing devices as slave devices and wherein the multiplexing device acting as the clock master is operated in synchronization with a clock received from a network while the multiplexing devices acting as the slave devices receive a clock from a clock transmission line of the extension bus which is outputted after the clock master has established synchronization with the network clock and regenerate a clock leading the received clock in phase.

Abstract: A data transfer apparatus and a data transfer system intended to transfer data continuously input or output to/from a main memory without any interruption and to transfer continuous data on a general-purpose bus such as a PCI bus, and a recording medium storing a program that commands a computer to execute all or some of functions of each component of the data transfer apparatus or the data transfer system.

Abstract: A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing. A storage device stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing. A counter updates a count value thereof every sampling period and generates the updated count value as a basic address.

Abstract: A method and apparatus for configuring multiple devices in a computer system is presented. Upon receipt of a device enumeration request corresponding to a first device, an indication that the first device is inoperable is returned. In response to a second device enumeration request corresponding to a second device, an indication of the capabilities of the second device is returned. When a configuration command corresponding to the second device is received, configuration information derived based on the configuration command is provided to both the first and second devices such that uniform parameter configuration is achieved with respect to the first and second devices. Because the operating system that issues the device enumeration request is informed that the first device is inoperable, the first device will be rendered unconfigurable and therefore configuration commands addressed to the first device will not be generated by the operating system.