Patents Examined by Mohammad R Alam
  • Patent number: 10734373
    Abstract: A circuit block including standard cells (1) arranged therein is provided with switch cells (20) capable of switching between electrical connection and disconnection between power supply lines (3) extending in an X-direction and power supply straps (11) extending in a Y-direction. Each of the power supply straps (11) is provided with a single switch cell (20) arranged every M sets of power supply lines (3) (M is an integer of 3 or more). In the Y-direction, the switch cells (20) are arranged at different positions in the power supply straps (11) adjacent to each other, and are arranged at the same position every M power supply straps (11) in the X-direction.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 4, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Atsushi Okamoto, Tomoyasu Kitaura, Hirotaka Takeno
  • Patent number: 10354873
    Abstract: Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objecti
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Akiteru Ko, Angelique Raley, Sophie Thibaut, Satoru Nakamura, Nihar Mohanty
  • Patent number: 10261248
    Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao