Abstract: A display apparatus includes: a first semiconductor substrate that includes a light emitting unit and a first drive circuit, the first drive circuit driving the light emitting unit; and a second semiconductor substrate that includes a second drive circuit to be electrically connected to the first drive circuit, the second semiconductor substrate being bonded to the first semiconductor substrate.

Abstract: An organic light emitting diode and a manufacturing method thereof, and a display panel are provided. The organic light emitting diode includes an anode layer, a hole transport layer, and a hole injection layer located between the anode layer and the hole transport layer. The hole injection layer has a work function of which a value increases in a direction from the anode layer toward the hole transport layer, and thus, an injection barrier between the anode layer and the hole transport layer is reduced and thereby improving the luminescent efficiency of the organic light emitting diode.

Abstract: A gate structure includes a first gate electrode including a metal, a gate barrier pattern on the first gate electrode and including a metal nitride, and a second gate electrode on the gate barrier pattern. The gate structure is buried in an upper portion of a substrate. The gate barrier pattern has a flat upper surface and an uneven lower surface.

Abstract: The present invention provides a device having a trench gate structure and a method of making the same. The device comprises a substrate, a drift region, a well region, a trench gate, a heavily-doped region, and an electrode positioned on the heavily-doped region. The structure of the device is simple to provide good VDMOS and IGBT breakdown voltages, and meanwhile take on-state resistance and reliability of oxide into account.

Abstract: The disclosure relates to an organic light emitting diode, a method for manufacturing the same, and a display panel. The organic light emitting diode includes: a first electrode; a second electrode disposed opposite to the first electrode; a light-emitting layer between the first electrode and the second electrode; the light-emitting layer includes a first light-emitting sub-layer and a second light-emitting sub-layer; the first light-emitting sub-layer includes a host material, a TADF sensitizer and a fluorescent guest material; the second light-emitting sub-layer includes the host material or includes the host material and the TADF sensitizer.

Abstract: An electroluminescent device, a method for manufacturing the electroluminescent device, a display panel and a display device are provided in the embodiments of the present application. The electroluminescent device includes an anode layer, a first hole injection layer and a hole transport layer. The first hole injection layer is located between the anode layer and the hole transport layer; the first hole injection layer includes at least two secondary hole injection layers, and an equivalent resistance value of the at least two secondary hole injection layers is greater than a first threshold value.

Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

Abstract: An apparatus includes a pixel that includes a current path including a light emitting element and a first transistor, a second transistor, and a third transistor connected to a signal wire. One of source and drain regions of the second transistor is connected to one node of the light emitting element and a first power supply. One of source and drain regions of the third transistor is connected to a gate electrode of the first transistor. An isolation portion is disposed between a first conductivity type first diffusion region that makes up one of the source and drain regions of the second transistor and a first conductivity type second diffusion region that makes up one of the source and drain regions of the third transistor. A depth of the first diffusion region is greater than a depth of the second diffusion region.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: A light-emitting display device includes: a substrate, a plurality of pixels on the substrate, each pixel including an opening area, a light extraction pattern disposed in each opening area, the light extraction pattern including: a plurality of concave portions spaced apart from each other, and a protruding portion surrounding each of the plurality of concave portions, and a light-emitting device layer including: a light-emitting layer over the light extraction pattern, and a non-emission area overlapping a top portion of the protruding portion between the two adjacent concave portions.

Abstract: A light emitting display apparatus includes a substrate including a plurality of pixels each including an emission area; a light extraction pattern including a plurality of concave portions in the emission area; and a light emitting portion over the light extraction pattern, wherein at least one of the plurality of concave portions has a curvature of 0.217 ?m?1 to 0.311 ?m?1.

Abstract: In method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.

Abstract: A semiconductor device according to an embodiment includes a lower layer wiring and a dummy wiring arranged in a first hierarchy, a contact arranged in a second hierarchy above the first hierarchy and connected to the lower layer wiring, and first and second plate-like portions arranged in the second hierarchy, extending in a stacking direction of each layer belonging to the second hierarchy and in a first direction intersecting with the stacking direction, and sandwiching the contact in a second direction intersecting with the stacking direction and the first direction at a position away from the contact, and the dummy wiring has at least three edges arranged at respective positions overlapping with one of the first and second plate-like portions in the stacking direction, and an orientation in which at least one of the three edges intersects with the first or second plate-like portion differs as viewed from the stacking direction from orientations in which the other edges intersect with the first or second

Abstract: Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.

Abstract: A contact structure and a manufacturing method are provided. The contact structure includes a recessed structure, a conductive feature, a first functional layer, a second functional layer and an interfacial layer. The conductive feature is filled in a recess of the recessed structure. The first functional layer extends between the conductive feature and the recessed structure. The second functional layer extends between the first functional layer and the conductive feature. The interfacial extends along an interface between the first and second functional layers, and includes a first element from the first functional layer and a second element from the second functional layer.

Abstract: The present invention is a laminate including: a crystal substrate; a middle layer formed on a main surface of the crystal substrate, the middle layer containing a mixture of an amorphous region in an amorphous phase and a crystal region in a crystal phase having a corundum structure mainly made of a first metal oxide; and a crystal layer formed on the middle layer and having a corundum structure mainly made of a second metal oxide. Thus, provided is a laminate having high-quality corundum-structured crystal with sufficiently suppressed crystal defects.

Abstract: Some implementations described herein provide a semiconductor device that includes a first set of gate-all-around (GAA) structures, having a first gate pitch, that includes a first set of source/drains having a first source/drain width and a first set of top spacers, having a first spacer width, disposed between a first set of gates of the first set of GAA structures and the first set of source/drains. The semiconductor device includes a second set of GAA structures having a second gate pitch, that, includes a second set of source/drains having a second source/drain width and a second set of top spacers, having a second spacer width, disposed between a second set of gates of the second set of GAA structures and the second set of source/drains.

Abstract: A light emitting diode (LED) having an active region and a three-dimensional (3D) structure. The 3D LED includes a first GaN-based layer having a first content of Aluminium and a first content of Indium, and a second GaN-based layer interposed between and in contact with the first layer and the active region, having a second content of Aluminium and a second content of Indium, the second content of indium being strictly higher than the first content of indium so as to promote the formation of misfit dislocations at an interface between the first and second layers. Advantageously, the active region and the first and second layers extend along semi-polar crystallographic planes. Also described is a method for manufacturing such a 3D LED.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.

Abstract: The disclosure provides a light-emitting device and a displayer. Herein, the light-emitting device includes a substrate, a light-emitting chip, a first light-transmitting layer, a second light-transmitting layer and a nano coating. The light transmittance of the second light-transmitting layer is greater than the light transmittance of the first light-transmitting layer. A reference surface corresponding to the light-emitting chip is arranged above the substrate, and the reference surface is higher than the bottom surface of the light-emitting chip and not higher than the top surface of the light-emitting chip. The first light-transmitting layer covers the surface of the light-emitting chip below the reference surface, and the second light-transmitting layer covers the surface of the light-emitting chip above the reference surface. The nano coating covers the outer surface of the first light-transmitting layer, the outer surface of the second light-transmitting layer and the side surface of the substrate.