Abstract: The present invention introduces a new shielded gate trench MOSFETs with improved specific on-resistance and avalanche capability structures including an active area and an edge termination area, wherein an epitaxial layer having special multiple stepped epitaxial (MSE) layers in an oxide charge balance (OCB) region, and an edge termination having multiple trench field plates, and electric field reducing regions disposed surrounding bottom of gate trenches with a doping concentration lower than said bottom epitaxial layer of the MSE layers. Moreover, in some preferred embodiment, a multiple stepped oxide structure in the OCB region, and an epitaxial layer in a buffer region below the OCB region with a doping concentration lower than the MSE layers is introduced to further reduce the specific on-resistance and enhance device ruggedness.

Abstract: A semiconductor device includes: a lower wiring including: a lower filling film, which extends in a first direction and includes a first portion having a first width in the first direction and a second portion, having a second width smaller than the first width in the first direction, on the first portion; and a lower barrier film which is disposed on a side wall and a bottom surface of the first portion, and is not disposed on a side wall of the second portion in a cross-sectional view of the first direction; and an upper wiring structure including: an upper via connected to the lower wiring; and an upper wiring extending in a second direction intersecting the first direction on the upper via, wherein the upper wiring structure further includes an upper barrier film, and an upper filling film in a trench defined by the upper barrier film, each of the upper via and the upper wiring comprises the upper barrier film and the upper filling film, and the upper via is not separated from the upper wiring by the uppe

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Abstract: A light source includes an epitaxial layer stack that includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer. The epitaxial layer stack includes a two-dimensional (2-D) array of mesa structures formed therein. The light source further includes an array of p-contacts electrically coupled to the p-type semiconductor layer of the 2-D array of mesa structures, a metal layer in regions surrounding individual mesa structures of the 2-D array of mesa structures, and a plurality of n-contacts coupling the metal layer to the n-type semiconductor layer at a plurality of locations between the individual mesa structures of the 2-D array of mesa structures.

Abstract: A display apparatus includes a substrate having an opening, a display area around the opening, and a middle area between the opening and the display area, a light-emitting element in the display area, the light-emitting element comprising a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode, and a disconnection portion in the middle area, the disconnection portion including a first stack structure and a second stack structure on the first stack structure. A 1-1st sub-layer, a 1-2nd sub-layer, and a 1-3rd sub-layer are sequentially stacked in the first stack structure. A 2-1st sub-layer, a 2-2nd sub-layer, and a 2-3rd sub-layer are sequentially stacked in the second stack structure. The intermediate layer and the opposite electrode extend from the display area to the middle area, the intermediate layer and the opposite electrode being disconnected at the disconnection portion.

Abstract: Implementations of semiconductor packages may include: a substrate having a first side and a second side and a die having an active area on a second side of the die. A first side of the die may be coupled to the second side of the substrate. The semiconductor package may also include a glass lid having a first side and a second side. The glass lid may be coupled over a second side of the die. The semiconductor package may include a first and a second molding compound and one or more cushions positioned between a first side of the glass lid and a portion of the first molding compound. The second molding compound may be coupled to the substrate and the around the die and the glass lid.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

Abstract: A thin film transistor, including: at least one active layer pattern including a first conductive pattern, a second conductive pattern, and a semiconductor pattern; a gate on a side of the active layer pattern; a first electrode and a second electrode on a side of the gate away from the active layer pattern, and respectively electrically connected with the first conductive pattern and the second conductive pattern, a conductive shielding pattern is provided corresponding to the semiconductor pattern in at least one active layer pattern, the conductive shielding pattern is on a side of the semiconductor pattern away from the gate and is electrically connected with the first electrode, and a buffer layer is between the conductive shielding pattern and the semiconductor pattern; an orthographic projection of the conductive shielding pattern on a plane where the semiconductor pattern corresponding thereto is located at least partially covers the semiconductor pattern corresponding.

Abstract: Light-emitting diode (LED) packages, and more particularly arrangements of light-altering coatings in LED packages are disclosed. Exemplary LED packages may include lead frame structures that are at least partially encased by a housing. Arrangements of light-altering coatings may be provided that cover one or more portions of lead frame structures exposed within LED package recesses. By providing light-altering coatings that cover lead frame structures within package recesses, negative impacts from potential lead frame discoloration due to environmental exposure may be reduced. Additionally, such light-altering coatings may be configured to reflect light emissions from LED chips before reaching portions of lead frame structures. Light-altering coating arrangements are disclosed where light-altering coatings are arranged in contact with LED chips or, alternatively, in a spaced relationship with LED chips.

Abstract: A polysilicon layer includes a polysilicon part of a polysilicon thin-film transistor. A first conductor layer includes a first gate electrode part of the polysilicon thin-film transistor. The first insulator layer includes a first insulator part located between the first gate electrode part and the polysilicon part. The oxide semiconductor layer includes an oxide semiconductor part of an oxide semiconductor thin-film transistor. The second conductor layer includes a second gate electrode part of the oxide semiconductor thin-film transistor. The second insulator layer includes a second insulator part located between the second gate electrode part and the oxide semiconductor part. The second insulator layer has a relative permittivity of not less than 8. The entire area of the second insulator layer is covered with the second conductor layer.

Abstract: A light emitting display panel and a device light emitting display device including the same including a substrate, a thin film transistor disposed on the substrate layer and comprising a first active layer a first gate electrode and the first electrode pattern, a first insulating layer disposed on the thin film transistor, a conductive pattern disposed on the first insulation layer, a second insulating layer disposed on the conductive pattern, a first electrode disposed on the second insulating film, and contacted to the first electrode pattern, and a bank exposing a portion of the top surface of the first electrode, wherein the first electrode and the conducting pattern is used as an electrode of storage capacitor and the conducting pattern is overlapped with a top surface of the first electrode not overlapped with the bank.

Abstract: A display device and a tiled display including the same are provided. The display device includes a bottom plate, and a display panel including an active area on the bottom plate and including a plurality of pixels, and a plurality of dummy areas near the active area and including a plurality of dummy pixels, wherein the plurality of dummy pixels is on at least one side surface of the bottom plate, wherein the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel configured to emit lights of different colors, and wherein the plurality of dummy pixels is configured to emit light of a same color as one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

Abstract: The disclosure provides a display panel, a compensation of brightness method and a displaying device. The display panel comprises an array substrate, a luminescent layer, a plurality of optical film layers and a photoelectric sensor, wherein the luminescent layer is located on one side of the array substrate, the array substrate is used for driving the luminescent layer to emit light, the optical film layers are located on a side, away from the array substrate, of the luminescent layer, light emitted by the luminescent layer forms optical waveguide on the array substrate and/or the optical film layers, and the photoelectric sensor is used for acquiring the optical waveguide to perform compensation of brightness on the light emitted by the luminescent layer according to data of the optical waveguide.

Abstract: A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each including a light receiving region disposed at a first principal surface side of the semiconductor substrate, the avalanche photodiodes being arranged two-dimensionally at the semiconductor substrate, and a through-electrode electrically connected to a corresponding light receiving region. The through-electrode is provided in a through-hole penetrating through the semiconductor substrate in an area where the plurality of avalanche photodiodes are arranged two-dimensionally. At the first principal surface side of the semiconductor substrate, a groove surrounding the through-hole is formed between the through-hole and the light receiving region adjacent to the through-hole.

Abstract: A display device in accordance with some embodiments may include a base layer, a first bank pattern and a second bank pattern on the base layer, and spaced apart from each other in a first direction, a first electrode overlapping the first bank pattern, a second electrode overlapping the second bank pattern, and a light emitting element aligned between the first electrode and the second electrode, wherein a distance between an end of the first electrode and an end of the first bank pattern differs from a distance between an end of the second electrode and an end of the second bank pattern in the first direction.

Abstract: A display apparatus includes a substrate having an opening, a display area around the opening, and a middle area between the opening and the display area, a light-emitting element in the display area, the light-emitting element comprising a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode, and a disconnection portion in the middle area, the disconnection portion including a first stack structure and a second stack structure on the first stack structure. A 1-1st sub-layer, a 1-2nd sub-layer, and a 1-3rd sub-layer are sequentially stacked in the first stack structure. A 2-1st sub-layer, a 2-2nd sub-layer, and a 2-3rd sub-layer are sequentially stacked in the second stack structure. The intermediate layer and the opposite electrode extend from the display area to the middle area, the intermediate layer and the opposite electrode being disconnected at the disconnection portion.

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked in a first direction on the first region and each including a pad region having an upper surface exposed upwardly in the second region, channel structures penetrating the gate electrodes and extending in the first direction, separation regions penetrating the gate electrodes and extending in the second direction, contact plugs each penetrating the pad region of each of the gate electrodes and extending in the first direction, a nitride layer disposed in an external side of a lowermost first gate electrode among the gate electrodes, spaced apart from the lowermost first gate electrode, and extending horizontally, and a dummy gate electrode disposed between the lowermost first gate electrode and the nitride layer in the second direction and having a first end spaced apart from the lowermost first gate electrode.

Abstract: A semiconductor device including a peripheral circuit structure on a substrate, a horizontal layer on the peripheral circuit structure, an electrode structure including electrodes on the horizontal layer, the electrodes including pads arranged in a stepwise shape, a planarization insulating layer covering the pads, a contact plug penetrating the planarization insulating layer and coupled to one of the pads, a penetration via penetrating the planarization insulating layer and coupled to the peripheral circuit structure, and a vertical conductive structure between the electrode structure and the penetration via may be provided. The vertical conductive structure may have a bottom surface located at a level that is higher than a top surface of the horizontal layer and is lower than a bottom end of the contact plug.