Abstract: A display device in accordance with some embodiments may include a base layer, a first bank pattern and a second bank pattern on the base layer, and spaced apart from each other in a first direction, a first electrode overlapping the first bank pattern, a second electrode overlapping the second bank pattern, and a light emitting element aligned between the first electrode and the second electrode, wherein a distance between an end of the first electrode and an end of the first bank pattern differs from a distance between an end of the second electrode and an end of the second bank pattern in the first direction.

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

Abstract: A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each including a light receiving region disposed at a first principal surface side of the semiconductor substrate, the avalanche photodiodes being arranged two-dimensionally at the semiconductor substrate, and a through-electrode electrically connected to a corresponding light receiving region. The through-electrode is provided in a through-hole penetrating through the semiconductor substrate in an area where the plurality of avalanche photodiodes are arranged two-dimensionally. At the first principal surface side of the semiconductor substrate, a groove surrounding the through-hole is formed between the through-hole and the light receiving region adjacent to the through-hole.

Abstract: The disclosure provides a display panel, a compensation of brightness method and a displaying device. The display panel comprises an array substrate, a luminescent layer, a plurality of optical film layers and a photoelectric sensor, wherein the luminescent layer is located on one side of the array substrate, the array substrate is used for driving the luminescent layer to emit light, the optical film layers are located on a side, away from the array substrate, of the luminescent layer, light emitted by the luminescent layer forms optical waveguide on the array substrate and/or the optical film layers, and the photoelectric sensor is used for acquiring the optical waveguide to perform compensation of brightness on the light emitted by the luminescent layer according to data of the optical waveguide.

Abstract: A display apparatus includes a substrate having an opening, a display area around the opening, and a middle area between the opening and the display area, a light-emitting element in the display area, the light-emitting element comprising a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode, and a disconnection portion in the middle area, the disconnection portion including a first stack structure and a second stack structure on the first stack structure. A 1-1st sub-layer, a 1-2nd sub-layer, and a 1-3rd sub-layer are sequentially stacked in the first stack structure. A 2-1st sub-layer, a 2-2nd sub-layer, and a 2-3rd sub-layer are sequentially stacked in the second stack structure. The intermediate layer and the opposite electrode extend from the display area to the middle area, the intermediate layer and the opposite electrode being disconnected at the disconnection portion.

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked in a first direction on the first region and each including a pad region having an upper surface exposed upwardly in the second region, channel structures penetrating the gate electrodes and extending in the first direction, separation regions penetrating the gate electrodes and extending in the second direction, contact plugs each penetrating the pad region of each of the gate electrodes and extending in the first direction, a nitride layer disposed in an external side of a lowermost first gate electrode among the gate electrodes, spaced apart from the lowermost first gate electrode, and extending horizontally, and a dummy gate electrode disposed between the lowermost first gate electrode and the nitride layer in the second direction and having a first end spaced apart from the lowermost first gate electrode.

Abstract: A semiconductor device including a peripheral circuit structure on a substrate, a horizontal layer on the peripheral circuit structure, an electrode structure including electrodes on the horizontal layer, the electrodes including pads arranged in a stepwise shape, a planarization insulating layer covering the pads, a contact plug penetrating the planarization insulating layer and coupled to one of the pads, a penetration via penetrating the planarization insulating layer and coupled to the peripheral circuit structure, and a vertical conductive structure between the electrode structure and the penetration via may be provided. The vertical conductive structure may have a bottom surface located at a level that is higher than a top surface of the horizontal layer and is lower than a bottom end of the contact plug.

Abstract: A display panel is provided. The display panel includes a base substrate and a plurality of display units disposed on the base substrate. The display unit includes a signal line, a light-emitting device and a drive unit. The light-emitting device is disposed in a flexible display region of the base substrate, the drive unit is disposed in a pixel circuit region of the base substrate, and the signal line is connected with the light-emitting device and the drive unit.

Abstract: Process flow for a stacked power diode and design of the resulting diode is disclosed. Blanket epitaxy over heavy doped wafers is performed. By controlling dopant addition during epitaxy, desired n-type, diode base, and p-type doping profiles and thicknesses achieved. V-groove pattern if formed on wafers by depositing mask film, lithography and anisotropic etch. Islands surrounded by V-grooves define individual diodes. V-grooves serve as side insulation. Next, oxidation step passivates V-grooves. Further, the mask film is stripped to open diode contact areas on both sides of wafers. Next high melting point metal and low melting point metal films are selectively electroplated on all open silicon surfaces. Stacking is performed on wafer level by bonding of desired wafer count by solid-liquid interdiffusion process. Wafer stacks are sawed into individual stacked diode dies along outer slopes of V-grooves. Final stacked devices can be used as DSRD—drift step recovery diodes.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A pattern of microchannels is formed on a major surface of a substrate on the side opposite an adhesive surface thereof. Through holes extend through the substrate and are connected to the pattern of microchannels. Solid circuit dies are adhesively bonded to the adhesive surface of the substrate. The contact pads of the solid circuit dies at least partially overlie and face the through holes. Electrically conductive channel traces are formed to electrically connect to the solid circuit dies via the through holes.

Abstract: A light emitting device package includes a package substrate, a semiconductor light emitting device on the package substrate, the semiconductor light emitting device including a substrate with a light emitting structure, a wavelength conversion portion on the semiconductor light emitting device, the wavelength conversion portion including a first region overlapping the light emitting structure, and a second region other than the first region, an adhesive layer between the semiconductor light emitting device and the wavelength conversion portion, and a reflective resin portion on the package substrate, the reflective resin portion surrounding the semiconductor light emitting device and the wavelength conversion portion, and the reflective resin portion extending to the second region.

Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

Abstract: An apparatus includes a baseplate and a cooler providing a cooling channel adapted for providing a coolant flow. An electronic circuit includes a power semiconductor device disposed at the first side of baseplate. A footprint of the power semiconductor device defines a device area on the first side. A cooling area at the second side of the baseplate opposite the device area is adapted for dissipating heat from the baseplate by bringing the cooling area into thermal contact with the coolant flow in the cooling channel. An auxiliary area is located on the second side of the baseplate adjacent to the cooling area. The auxiliary area includes a flow guide for reducing a flow rate of the coolant flow in the auxiliary area and the cooling channel is adapted to receive the cooling area and the flow guide.

Abstract: A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.

Abstract: A lighting device disclosed in an embodiment of the invention includes: a lighting module emitting a first light and a second light; and a lens disposed on the lighting module to block light of a shorter wavelength among the first light and the second light and transmit light of a longer wavelength, wherein the lighting module includes: a substrate; a plurality of light emitting devices disposed on the substrate and emitting a first light; a resin layer covering the plurality of light emitting devices; and a phosphor layer disposed on the resin layer to convert the first light into second light, wherein the first and second light travel through the phosphor layer in the lens direction, and the second light may pass through the lens.

Abstract: A display panel and a display device are provided. The display panel includes first, second and third data lines located in a display area, first and second compensation capacitors located in a first non-display area and have a same capacitance, and a peripheral circuit located in a second non-display area. The first and second data lines are electrically connected to M sub-pixels, and the third data line is electrically connected to N sub-pixels, where 1?M<N, M and N are integers. The first and second compensation capacitors are electrically connected to the first and second data lines, respectively. The first non-display area has a length gradually decreasing along a direction parallel to the first direction and along a direction from the display area to the second non-display area, and the length is a size of the first non-display area along the second direction.

Abstract: Horizontal Cavity Surface Emitting Lasers (HCSELs) with angled facets may be fabricated by a chemical or physical etching process, and the epitaxially grown semiconductor device layers may be transferred through a selective etch and release process from their original epitaxial substrate to a carrier wafer.

Abstract: A COB type photoelectric device is provided. The COB type photoelectric device includes: a metallic substrate including a photoelectric element fixing area; a dam disposed on the metallic substrate and surrounding the photoelectric element fixing area; first photoelectric elements disposed on the metallic substrate and in the photoelectric element fixing area; a KSF phosphor based layer disposed on the first photoelectric elements and being not in contact with the metallic substrate; and an isolation layer disposed in the dam and covering the KSF phosphor based layer. The KSF phosphor based layer includes a KSF phosphor. The COB type photoelectric device can make full use of high luminous efficiency performance of the KSF, and improve luminous efficiency of the COB type photoelectric device while maintaining stability of the KSF.

Abstract: An organic light emitting diode and a manufacturing method thereof, and a display panel are provided. The organic light emitting diode includes an anode layer, a hole transport layer, and a hole injection layer located between the anode layer and the hole transport layer. The hole injection layer has a work function of which a value increases in a direction from the anode layer toward the hole transport layer, and thus, an injection barrier between the anode layer and the hole transport layer is reduced and thereby improving the luminescent efficiency of the organic light emitting diode.