Abstract: The disclosure provides a light-emitting device and a displayer. Herein, the light-emitting device includes a substrate, a light-emitting chip, a first light-transmitting layer, a second light-transmitting layer and a nano coating. The light transmittance of the second light-transmitting layer is greater than the light transmittance of the first light-transmitting layer. A reference surface corresponding to the light-emitting chip is arranged above the substrate, and the reference surface is higher than the bottom surface of the light-emitting chip and not higher than the top surface of the light-emitting chip. The first light-transmitting layer covers the surface of the light-emitting chip below the reference surface, and the second light-transmitting layer covers the surface of the light-emitting chip above the reference surface. The nano coating covers the outer surface of the first light-transmitting layer, the outer surface of the second light-transmitting layer and the side surface of the substrate.

Abstract: A transistor device including source and drain electrodes, a fin structure extending between and contacting respective sidewalls of the source and drain electrodes, a semiconductor channel layer over the upper surface and side surfaces of the fin structure and including a first and second vertical portions over the side surfaces of the fin structure, and the first and second vertical portions of the semiconductor channel layer both contact the respective sidewalls of the source electrode and the drain electrode, a gate dielectric layer over the semiconductor channel layer, and a gate electrode over the gate dielectric layer. By forming the semiconductor channel layer over a fin structure extending between sidewalls of the source and drain electrodes, a contact area between the semiconductor channel and the source and drain electrodes may be increased, which may provide increased driving current for the transistor device without increasing the device size.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures suspended over a substrate and multiple second semiconductor nanostructures suspended over the substrate. The semiconductor device structure also includes a dielectric fin between the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a metal gate stack wrapped around the dielectric fin, the first semiconductor nanostructures and the second semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode, and the gate dielectric layer extends along a sidewall and a topmost surface of the dielectric fin.

Abstract: In an embodiment an optoelectronic component includes a first joining partner including an LED chip with a structured light-emitting surface and a compensation layer applied to the light-emitting surface, wherein the compensation layer has a surface facing away from the light-emitting surface and spaced apart from the light-emitting surface, and wherein the surface forms a first connecting surface, a second joining partner having a second connecting surface, the first and second connecting surfaces being arranged such that they face each other and a bonding layer made of a film of low-melting glass having a layer thickness of not more than 1 ?m, wherein the bonding layer bonds the first and second connecting surfaces together, wherein the structure of the light-emitting surface is embedded in the compensation layer, and wherein the first and second connecting surfaces are smooth such that their surface roughness, expressed as center-line roughness, is less than or equal to 50 nm.

Abstract: An image sensing device includes a first substrate layer including first conductive impurities and structured to produce photocharges based on the incident light and capture the photocharges using a voltage difference induced in response to a demodulation control signal; a second substrate layer including second conductive impurities having characteristics opposite to those of the first conductive impurities, and structured to be bonded to the first substrate layer; and a depletion layer formed between the first substrate layer and the second substrate layer.

Abstract: A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

Abstract: A capacitance structure and a forming method thereof are provided, and the forming method includes: an annular gasket is formed on a substrate, and after a central through hole exposing a part of a surface of the substrate is formed in a center of the annular gasket, a first capacitance structure is formed in the central through hole; a dielectric layer covering the substrate, the annular gasket and the first capacitance structure is formed; the dielectric layer is etched to form an etching hole communicating with the central through hole in the dielectric layer; and a second capacitance structure connected to the first capacitance structure is formed in the etching hole.

Abstract: A display panel and a display device capable of reducing peeling due to a decrease in interlayer adhesion by direct contact of a color filter with a first insulating layer are provided.

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

Abstract: A display device is provided. The display device includes a substrate, a first electrode, a second electrode, and third electrode spaced apart from each other in a first direction on the substrate, a repair line spaced apart from the first to third electrodes in the first direction on the substrate, a repair connection portion connecting the third electrode and the repair line, and light emitting elements on respective ones of the first to third electrodes and spaced apart from each other.

Abstract: Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.

Abstract: A cover plate and a display device is provided. The cover plate includes a first cover plate layer and a second cover plate layer. The first cover plate layer is located on a light entry side of the cover plate. The second cover plate layer is located on a light exit side of the cover plate and attached to a first surface of the first cover plate layer. A plurality of protrusions are disposed on the first surface of the first cover plate layer. A refractive index of the first cover plate layer is less than a refractive index of the second cover plate layer.

Abstract: Provided is a three-dimensional flash memory including a substrate, a stack structure, a stop layer, two slit trenches, a plurality of vertical channel structures, and a plurality of slit holes. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The stop layer is disposed between the substrate and the stack structure. The two slit trenches penetrate through the stack structure to expose the stop layer. The vertical channel structures are disposed between the two slit trenches and penetrate through the stack structure and the stop layer. The slit holes are discretely disposed between the vertical channel structures, and penetrate through the stack structure to expose the stop layer. A method of forming the three-dimensional flash memory is also provided.

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

Abstract: A display device includes first banks on a substrate and spaced apart from each other, a first electrode and a second electrode on the first banks and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, and light emitting elements on the first insulating layer and each having ends on the first electrode and the second electrode. Each of the first banks includes a first pattern portion including concave portions and convex portions. The first pattern portions of the first banks are disposed on side surfaces of the first banks. The side surfaces are spaced apart and face each other. Each of the first electrode and the second electrode includes a second pattern portion on the first pattern portion and having a pattern shape corresponding to the first pattern portion on a surface thereof.

Abstract: Provided are a display panel and a display device. The display panel includes a substrate, a driving circuit layer disposed on the substrate and including driving circuits, LED chips located on side of the drive circuit layer facing away from the substrate and each electrically connected to a corresponding drive circuit, the drive circuit includes at least one first thin film transistor with a source and a drain located at first metal layer of the drive circuit layer and electrically connected to first electrode of corresponding LED chip, and at least part of edges of the display panel is provided with thermally conductive adhesive. The substrate is also provided with one or more layers of thermally conductive metal, at least one layer of thermally conductive metal extends to the edges of the display panel and is in contact with the thermally conductive adhesive.

Abstract: A method for manufacturing an electronic device includes at least a preparing step of preparing a structure provided with an adhesive film provided with a base material layer, an adhesive resin layer (A) provided on a first surface side of the base material layer, an adhesive resin layer (B) provided on a second surface side of the base material layer and in which an adhesive force is reduced by external stimuli, and an unevenness-absorbing resin layer (C) provided between the base material layer and the adhesive resin layer (A) or between the base material layer and the adhesive resin layer (B), an electronic component attached to the adhesive resin layer (A) of the adhesive film and having an uneven structure, and a support substrate attached to the adhesive resin layer (B) of the adhesive film; and a sealing step of sealing the electronic component with a sealing material.

Abstract: A micro-LED device and a method of fabricating the micro-LED device are disclosed. The method includes processing from a first side (e.g., p-side) of epitaxial layers of a micro-LED wafer to form individual mesa structures and a first solid metal bonding layer on the mesa structures, bonding a second solid metal bonding layer on a backplane wafer to the first solid metal bonding layer of the micro-LED wafer, removing the substrate of the micro-LED wafer and processing from a second side (e.g., n-side) of the epitaxial layers to isolate the solid metal bonding layers and form individual electrodes (e.g., anodes) for individual micro-LEDs, forming a dielectric material layer on surfaces in regions between the mesa structures, and depositing one or more metal materials in the regions between the mesa structures to form mesa sidewall reflectors and a common electrode for the micro-LEDs.

Abstract: Disclosed are a light-emitting substrate and a display device. In the light-emitting substrate, a first pad of a light-emitting area includes a first metal layer located above a base substrate and a second metal layer located on a side, facing away from the base substrate, of the first metal layer. A material of the second metal layer includes copper-nickel-titanium alloy, and a quantity of nickel atoms and/or titanium atoms contained per unit area in a cross section, farther from the base substrate, of the second metal layer is greater than a quantity of nickel atoms and/or titanium atoms contained per unit area in another cross section, closer to the base substrate, of the second metal layer.