Abstract: A memory device having a plurality of cells, each of which stores a value, where the values of the cells are mapped to discrete levels and the discrete levels represent data, is programmed by determining a maximum number of cell levels in the memory device, and determining the set of values that are associated with each of the cell levels. The maximum number of cell levels for the memory device is determined by an adaptive programming system connected to the memory device, based on a plurality of cell values attained by at least one cell of the memory device, in response to voltage applied by the adaptive programming system to the cells of the memory device. The adaptive programming system associates, for each of the cell levels, a different set of cell values of the plurality of cell values attained by the cells to which voltage is applied.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.