Abstract: A narrowband interference excision method and apparatus. According to one embodiment, a method for narrowband interference excision is disclosed. The method comprising transforming time domain data into a frequency domain vector having a plurality of frequency bins. The method further comprises estimating a plurality of power values corresponding to frequency bins of the frequency domain vector to obtain a current power vector. Then, calculating an average power vector from the current power vector and at least one selected previous power vector. Further, excising selected frequency bins of the frequency domain vector to produce an excised frequency domain vector. Moreover, determining whether to include the average power vector in future average power vector determinations. In another embodiment, a narrowband interference excision apparatus is disclosed.

Abstract: A carrier recovery apparatus capable of detecting a phase error of modulation signal by a simple calculation, reducing the circuit scale, and improving the frequency capture characteristic and phase jitter characteristic is presented. This carrier recovery apparatus comprises a symbol estimating unit for estimating the transmitted symbol, a phase error detector for generating a normalized phase error signal on the basis of the estimated symbol and reception signal, a loop filter for filtering the phase error, and a numerical control oscillator controlled by the loop filter.

Abstract: A method for processing an input burst signal comprising a first step for identifying an additive DC component and generating an output signal, which is representative for an estimated value of said DC component. The method further comprises a second step for detecting a predetermined signal portion from a plurality of possible signal portions included in the input burst signal and generating a control signal indicating the presence of the predetermined signal portion in the input burst signal. The method is characterized in that the first step and the second step are performed in parallel i.e. in a commonly defined time interval from a starting time of the burst.

Abstract: The invention relates to a device for cancelling inter-symbol interference in a sampled digital signal. The device comprises a first filter, for which the optimum transfer function is identical to that of the transmission channel, and which receives a sequence of samples ({{tilde over (d)}n}n?N) representative of the digital signal sent to the input of the transmission channel, a subtractor circuit to subtract the first filter output ({{tilde over (d)}?n}n?N) from the sequence of input samples ({rn}n?N), a second filter tuned to the transmission channel, with an optimum transfer function H*(f), to which the output ({en}n?N) from the subtractor circuit is input, and an adder circuit designed to add the output from the second filter to the sequence of samples ({{tilde over (d)}n}n?N) representative of the digital signal sent to the input of the transmission channel, and thus generating a sequence of complex symbols ({n}n?N) without any inter-symbol interference.

Abstract: A series of digit processing units (DPUs) are connected to form a finite impulse response (FIR) filter. Each DPU includes a register, a multiplexer, and a coefficient multiplier. The register stores and delays an input digital signal to be filtered. The multiplexer has inputs connected to the input node and to an output of the register, an output of the multiplexer for connecting to a next stage DPU. The coefficient multiplier is connected to the output of the register and multiplies the input signal by a coefficient or part of a coefficient. A group of DPUs can have multiplexers set so that the register of each DPU stores the same part of the input signal for processing a single filter coefficient. An adder is provided to sum output of the DPUs and output a filtered signal. The critical path of the FIR filter is independent of coefficient number and precision.

Abstract: A method and system that communicates adaptive transmit-side filter updates between a receiver and transmitter inserts additional versions of control codes into a back channel for encoding updates. Since the control codes are required in the back channel, no additional bandwidth of the back channel is used to communicate the updates.

Abstract: A system and method are provided for transitioning between modulation formats in adjacent transmit bursts. The system includes a modulation system having a data interface, first modulation circuitry operating according to a first modulation format, and second modulation circuitry operating according to a second modulation format. During a transition between a first transmit burst in the first modulation format and a second transmit burst in the second modulation format, the data interface receives a timing signal signifying a start of data for the second transmit burst. In response to the timing signal, the second modulation circuitry resets, and the data interface delays the data for the second transmit burst by a modulator delay time. By delaying the data for the second transmit burst, a glitch caused by resetting the second modulation circuitry arrives at the output of the second modulation circuitry prior to the data for the second transmit burst.

Abstract: A radio transmitter and receiver arrangement includes a transmitter and a receiver. The transmitter generates an electromagnetic carrier that varies in frequency throughout a channel interval, and modulates the carrier with an information signal during the channel interval, whereby the carrier is modulated both in frequency and in accordance with the information signal during the channel interval. The receiver receives the carrier that is modulated both in frequency and in accordance with the information signal, generates a detection signal that varies in frequency throughout the channel interval, and mixes the carrier and the detection signal to recover the information signal.

Abstract: A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay elements, for delaying a digital estimate of a decision device; a second delay element chain having serially connected delay elements, for delaying an equalized signal; a multiplier array which multiplies the undelayed digital estimate and the delayed estimates of all the delay elements of the first delay element chain by the equalized signal and the delayed output signals of all the delay elements of the second delay element chain to generate product signals; a weighting circuit multiplies the product signals generated by the multiplier array by adjustable weighting factors; and having an adder which adds the product signals weighted by the weighting circuit to the sampling phase error signal.

Abstract: A method is provided to provide data to automatically estimate channel performance in a communication system if a different order constellation is used comprising the steps of: receiving an input signal from the channel; passing the input signal to a slicer having an output signal; determining signal noise by taking the difference between the input signal and output signal; identifying a beginning of a noise event when the signal noise is greater than a predefined first threshold; identifying an end of a noise event when the signal noise is less than a predefined second threshold; and providing for output the beginning of the noise event and the end of the noise event. Other systems and methods are disclosed.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: A system and method for channel estimation in a wireless local area network. A corresponding channel estimation method includes the steps of: receiving a preamble message and despreading the preamble message into several symbol signals, each symbol signal containing several discrete signals; determining for each symbol signal a peak sign assignment; establishing several data windows for the symbol signals at the starting points of the discrete signals; multiplying the discrete value of each discrete signal of each data window by the corresponding peak sign assignment and accumulating the product in the first data frame; repeating the above steps for the next discrete signal and accumulating them in the second data frame, . . . , the Nth data frame; computing the accumulated value in the data frames and obtaining the data frame with the maximum value; estimating a channel signal from the previously determined data frame.

Abstract: The invention intends to realize a high accuracy of some picoseconds in skew compensation as well as a downsized circuit scale. A phase shifter using analog circuits that allows a downsized circuit scale and a high-accuracy phase shifting is adopted in order to finely shift the phase between a clock signal and a data signal. The phase shifter passes the clock signal or the data signal through a low pass filter having a pass band not higher than the based frequency of the clock signal to extract the frequency factors not higher than the based frequency factors. After dividing the extracted signal into plural signals, the phase shifter inputs the clock signal or the data signal having the phase shifted to plural variable gain amplifiers. Next, the phase shifter inputs the outputs from the variable gain amplifiers to an adder or a subtracter, and inputs the signal after being added or subtracted to a limit amplifier to reshape it into a rectangular wave.

Abstract: A method of decoding data includes receiving a symbol and determining a data rate that was used to encode the symbol. A set of correlator output signals are generated based on a first mode when a first data rate was used to encode the symbol and based on a second mode when a second data rate was used to encode the symbol. A maximum-valued signal in one of the set of correlator output signals is identified. The maximum-valued signal in one of the set of correlator output signals is modulated.

Abstract: An algorithm for bit synchronization in a frequency shift keying (FSK) receiver. In the algorithm, a training sequence is received from a transmitter. The training sequence has a plurality of bits. A starting point of a next bit received by the FSK receiver after the training sequence is determined according to peak values of the bits of the training sequence.

Abstract: A signal is predistorted by producing a set of sample values, each of at least a subset of which is dependent on (i) at least one of a plurality of past time spaced input samples and (ii) a current time spaced input sample, and independent of any other time spaced input sample, and combining the sample values to produce the predistorted signal. Predistortion circuitry for generating the predistorted signal may be implemented using multiple predistortion core circuits, with each of the predistortion core circuits receiving a data input and an index input associated with a particular input sample and generating a corresponding data output. The data outputs of the predistortion core circuits correspond generally to sample values. The predistortion circuitry may also include at least one memory finite impulse response (FIR) filter which processes one or more input samples in conjunction with the production of the sample values.

Abstract: A phase interpolator includes a plurality of clock phase input sections, a plurality of clock phase switching sections, a plurality of current sources and a load. Each of the clock phase input sections is coupled to receive one of a plurality of reference clock phases (e.g., 0°, 90°, 180°, and 270°). The plurality of current sources is selectively coupled to the plurality of clock phase input sections via the clock phase switching sections based on a phase control signal. The number of current sources corresponds to the phase granularity between the reference clock phases. The load is coupled to a phase adjusted clock signal in accordance with the phase control signal.

Abstract: A multivalued FSK modulation system is provided in which when data to be transmitted is multivalued and transmitted/received, the detection level is different every symbol. When a two-valued signal is transmitted as one symbol, data (11), (01), (00) and (10) are previously set to be, for example, a shift of ?6, a shift of +6, a shift of +2, and a shift of ?2, respectively. When data to be input next is (00), mapping is performed so as to provide a sign weight of +2 from the sign weight at the position of current data. When the data to be input next is (10), mapping is performed so as to provide a sign weight of ?2 from the position of the current sign weight. Thus, even if data of the same level is input, signals can be always detected in different levels, so that the sign detection point is not specified erroneously.

Abstract: Techniques and instrumentalities to improve ISI and ICI cancellation in reception of modulated symbols by selectively decoding subsymbols of such modulated symbol before they can be completely decided or perceived as well as use of decoded symbol/subsymbol information in the feedback equalization process are disclosed. In particular, a decoder and corresponding method are disclosed which includes a feedback equalizer capable of receiving a modulated signal including a symbol defined by a first number of chips, along with a subsymbol processor to generate a subsymbol waveform upon receipt of a second number, less than the first number, of chips of such symbol and provide the subsymbol waveform to the feedback equalizer in order to equalize the modulated signal using the subsymbol waveform.

Abstract: A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for estimating the generation probability of the peak-to-peak value or peak value of the clock skews. The probability estimating apparatus for peak-to-peak values in clock skews includes a clock skew estimator for estimating clock skew sequences among the plurality of clock signals under test and a probability estimator for determining a generation probability of the peak-to-peak values in the clock skews among the plurality of clock signals under test based on the clock skew sequences from the clock skew estimator by applying Rayleigh distribution. The generation probability of the peak-to-peak value is estimated based on RMS values of the clock signals and the Rayleigh distribution.