Abstract: Received baseband signals from a plurality of antennas 111 to 11Q are linearly combined through multiplication by weighting coefficients, then a decision signal is delayed for one symbol duration, and the delayed signal is multiplied by a feedback filter coefficient wb* to generate intersymbol interference, which is subtracted from the linearly combined output y(i). The subtracted output is subjected to a signal decision to obtain a decision signal, then the difference between the input into a decision unit 17 and the decision signal is obtained as an error signal e(i), and weighting coefficients w1* to wQ* and the feedback filter coefficient wb* are estimated in a parameter estimation part 71 so that the square of the error signal e(i) is minimized.

Abstract: A transmitter within a line driver circuit is configured to supply data signals in compliance with the Multilevel Transmission-3 (MLT-3) protocol for high speed data communication. The transmitter comprises a pre-driver system and a final driver. The pre-driver system comprises a plurality of individual pre-drivers that are in parallel. A zero drive logic designates any number of individual pre-drivers as zero drive types, such that these designated zero drive pre-drivers are turned ON during a zero signaling state. The partially turned ON pre-driver system, during the zero state, permits the final driver to rapidly output positive and negative signals in accord with the MLT-3 protocol.

Abstract: A method for use with a computer system includes modulating a first clock signal according to a first frequency-time profile to generate a second spread spectrum clock signal. The first clock signal is modulated according to a second frequency-time profile that is asynchronous to the first frequency-time profile to generate a third spread spectrum clock signal.

Abstract: A spread spectrum demodulation circuit includes a correlation signal generator which generates a correlation signal from a reception signal to which a quadrature phase shift keying and a spread spectrum modulation are performed. First and second delay elements have different delay times, and delay the correlation signal to obtain first and second delay signals, respectively. First and second adders add the correlation signal and the first and second delay signals to obtain first and second addition signals, respectively. First and second distributors distribute the first and second addition signals, respectively. First and second multiplication circuits obtain first and second multiplication signals from distributed signals inputted from the first and second distributors, respectively. A data demodulation circuit demodulates the first and second multiplication signals to recover a transmission information signal.

Abstract: The present invention discloses an apparatus and a method for correcting the phase of a synchronizing signal. A best clock timing on latching the data input can be achieved by the apparatus and the method provided. The apparatus of the present invention includes: a phase adjusting circuit for adjusting the phase; a phase lock loop being responsive to the phase adjusting circuit for generating a clock pulse signal; a latching circuit for generating a latched data pattern of the data input; a comparing circuit for comparing the latched pattern with the data input; and a switching circuit for varying a time delay of the phase adjusting circuit. The method of the present invention includes the following steps. At first, the phase of the synchronizing signal is delayed and a clock pulse signal is generated from a phase delayed synchronizing signal. Next, a test pattern is latched as a latched pattern by referencing the clock pulse signal. The latched pattern is then compared with the test pattern.