Abstract: A multivalued FSK modulation system is provided in which when data to be transmitted is multivalued and transmitted/received, the detection level is different every symbol. When a two-valued signal is transmitted as one symbol, data (11), (01), (00) and (10) are previously set to be, for example, a shift of ?6, a shift of +6, a shift of +2, and a shift of ?2, respectively. When data to be input next is (00), mapping is performed so as to provide a sign weight of +2 from the sign weight at the position of current data. When the data to be input next is (10), mapping is performed so as to provide a sign weight of ?2 from the position of the current sign weight. Thus, even if data of the same level is input, signals can be always detected in different levels, so that the sign detection point is not specified erroneously.

Abstract: An analyzer transforms a digital signal into a spectrum representing the digital signal. A spectrum analyzing unit specifies a predetermined number of sets of the bands in decreasing order of the correlation between the spectrum distributions from among the bands obtained by equally dividing the above spectrum into equal bands, and then specifies one of the two specified bands as a removed band and the other as a interpolation band. Then, a frequency shifting unit removes spectrum components within the removed bands and shifts spectrum components within another bands to the lower frequency side (that is, performs the thinning and compressing of frequency), and then supplies a signal representing the spectrum after thinning and compressing to a synthesizer. The synthesizer generates a signal represented by the spectrum after thinning and compressing.

Abstract: A system and method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. In a system embodiment, a phase detector is provided for detecting a phase between the first and second clock signals. A skew state detector disposed in communication with the phase detector is operable to generate a skew state signal which tracks a phase relationship between the clock signals. A synchronizer control signal generator responds to the skew state signal by generating at least one control signal to compensate for the skew between the first clock signal and the second clock signal.

Abstract: A system and method for maintaining a stable synchronization state in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. In a system embodiment, a first circuit portion generates a load signal indicative of a known acceptable state for which a cycle can be loaded. A second circuit portion is in communication with the first circuit portion in order to generate a lock signal indicative of a tolerable tracked skew between a first clock signal of the first clock domain and a second clock signal of the second clock domain. A third circuit portion, responsive to the load signal, the lock signal and a zero skew point indicator, generates a synchronization stable state signal indicative of locking between the first clock signal and the second clock signal.