Abstract: A method of passing data between objects located distributed among a plurality of virtual address space domains established by processes executing on a data processing system comprises several steps. First, a session initiation message from a source object in a domain is broadcast to other objects in the domain. Responsive to receipt of the session initiation message by a domain agent (a type of object) for the domain, forwarding the session initiation message from the domain agent to each of a plurality of domain agents in other virtual address space domains. Responsive to receipt of the session initiation message by the domain agent for a second domain, transmitting the session initiation message from the domain agent for the second domain to an agent object in the second domain for the source object.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.

Abstract: A data processing system (10) capable of generating an output waveform (22) that has enhanced pulse width resolution. In one form, the system uses a counter (34) which is incremented by an input clock (20) running at an operating frequency of the system. Instead of incrementing the counter (34) by one, the counter (34) is incremented by a power of two so that the counter (34) appears to be counting a power of two faster. However, in order to increase the effective resolution of the counter (34), the second edge of the output waveform (22) must be correctly adjusted depending on the desired duty cycle and period. The end result is a counter (34) that can produce a power of two greater resolution while still using the operating frequency of the system as an input clock (20).

Abstract: Message-routing apparatus is known for routing messages between a plurality of communications networks. Typically, the known apparatus comprises a respective network interface card for each communications network and a shared, processor-based, routing manager with which the cards communicate through a backplane bus system. In order to overcome the bandwidth limitations of such known apparatus, the present invention provides a local routing manager on each card and high-speed, point-to-point, links interconnecting the local routing managers in a closed loop. Each local routing manager recognizes whether a message passed to it is for outward transmission over the associated network; if this is not the case, the message is passed to the local routing manager of the next card. Any messages which the local routing managers are unable to route, are diverted to a shared routing manager.

Abstract: An array controller including a novel data path structure for effecting data transfers between a host computer system bus and four array busses associated with a RAID level 3 disk array without the utilization of a buffer between the host system and the array. The data path structure includes a host register associated with each array bus, each host register being connected to the host bus for receiving data therefrom; a first array register associated with each array bus, each first array register being connected to a corresponding host register for receiving data therefrom and connected to its associated array bus for providing data thereto; and a second array register associated with each array bus, each second array register being connected to it associated array bus for receiving data therefrom and connected to the host bus for providing data thereto.

Abstract: A communication system containing a plurality of node elements. Each node element contains: a main communication unit containing a multiplexer/demultiplexer unit, a management control unit, a data input/output terminal unit, a switch unit, a connection mode control unit, and a link establishing unit. The connection mode control unit connects the data input/output terminal unit to either the management control unit in its own node element or another management control unit in another remote node element, by controlling the switch unit. The link establishing unit establishes a link for the data input/output terminal unit to access the management control unit in another remote node element through an overhead channel between the node elements.

Abstract: A satellite wide area communications network (10) includes a remote transmitter/receiver (28A) that is coupled through a modem unit (30A) to multiple card readers (12A-1 to 12A-n). A master transmitter/receiver (26) is satellite linked to the remote transmitter/receiver and is coupled through a central packet network (16) to multiple host computers (18-1 to 18-j). A network host computer address is determined for each transaction card inserted in the card readers, and the network address is processed to establish a direct link to the host computer for the card through the modem unit, the satellite link (22A, 20, 24), and the central packet network.

Abstract: A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of devices is described. The memory controller apparatus interfaces the microprocessor and the plurality of devices. The microprocessor functions asynchronously with the plurality of devices. The memory controller apparatus comprises a delay line circuitry coupled to receive a selected request for accessing the memory array from one of the microprocessor and the plurality of devices, the delay line means further including means for generating a plurality of memory timing control signals. The memory timing control signals are used for accessing the memory array. The delay line circuitry functions independently of any clock signal. The delay line circuitry is only triggered by the selected request. The memory controller apparatus further comprises a memory state circuitry coupled to the delay line circuitry for controlling sequence and timing of the memory timing control signals.

Abstract: An office communication system for transmitting data and/or video information through a communication network to a given device and at a given point in time. An automatic selection device is provided having a timer circuit with a calendar function which may be adjusted by the user along with control device. The automatic selecting device makes a connection through the communication network corresponding to the time desired by the user. A data transmission occurs through a communication interface means at a time which is cost favorable to the user.