Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

Abstract: A semiconductor device includes a plurality of wirings (WR11) which are formed in the same layer above a semiconductor substrate, and a plurality of wirings (WR12) which are formed in the same layer as that of the plurality of wirings (WR11). The plurality of wirings (WR11) are extended in an X axis direction and arranged at a pitch (PT11) in a Y axis direction intersecting with the X axis direction when seen in a plan view, and the plurality of wirings (WR12) are extended in the X axis direction and arranged at a pitch (PT12) in the Y axis direction when seen in a plan view. The plurality of wirings (WR11) are electrically connected to the plurality of wirings (WR12), and the pitch (PT11) is smaller than the pitch (PT12).

Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.