Abstract: A circuit for optimizing and adapting the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The circuit preferably includes a high speed memory coupled to a digital signal processor running an executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing initial and adaptive sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. The circuit keeps track of the number of non-zero bit sub-channels (N.sub.CH) from iteration to iteration, which results in a more accurate loading of the sub-channels.

Abstract: A synchronization method and apparatus for synchronizing a receiver, such as a radiotelephone operable in a cellular communication system with a transmitter. Synchronization sequences are transmitted as parts of a control signal to the receiver. The synchronization sequences are formed of either a dotting sequence or a set of m-sequences. Such synchronization sequences are of high margins and also permit synchronization of the user terminal responsive to a reduced number of calculations.

Abstract: There is disclosed a method and apparatus for computing branch metrics that are combinations of autocorrelation and cross correlation terms are constructed by first calculating and storing components of the autocorrelation and cross correlation terms at a symbol instant. Once calculated and stored, predetermined ones of the autocorrelation components and the cross correlation components are selected. The selected autocorrelation components and cross correlation components, or their inverse as predetermined, are combined to produce a branch metric. Other predetermined combinations of the stored components of autocorrelation and cross correlation terms, or their inverse, are combined to produce other branch metrics at the same symbol instant. All branch metrics associated with the symbol instant can be calculated in this manner.

Abstract: A demodulator of the present invention comprises a clock signal generator for generating a clock signal having a frequency that is 4 times n times (n is an integer greater than zero) the carrier frequency of a received signal, an analog-to-digital (A/D) converter for converting the received signal into a digital signal, a complex signal generator clocked by the clock signal to generate a complex signal comprised of the received signal as a real part and a .pi./2 phase-shifted signal as an imaginary part, a phase rotator for generating quasi-coherent detected signals by multiplying the complex signal by specific values of the carrier frequency, and a decimation circuit clocked by a clock signal to generate the required I channel signal and Q channel signal by decimating the quasi-coherent detected signals so as to finally obtain improved accuracy for accomplishing quadrature detection and eliminate an amplitude deviation and a direct-current offset.

Abstract: In accordance with one embodiment of the present invention, in a wireless telecommunications system, an automatic gain control loop for a base station, comprises a demodulator having at least one output terminal. The demodulator is adapted to demodulate signals received by the base station so as to provide a plurality of phase signals via its output terminals. These phase signals correspond to the phase of the signals received by the base station. A plurality of variable-gain amplifiers are adapted to receive one of the phase signals and to change the amplitude of said phase signals. A plurality of signal processing units are adapted so as to receive signals provided by the variable amplifiers, and each of the signal processing units is further adapted to generate a feedback control signal so as to control the gain of each one of the variable-gain amplifiers.

Abstract: A method of and an apparatus for phase synchronization of a bit rate clock signal generated in an RDS receiver with a digital RDS signal demodulated on the receiver side, in which both the bit rate clock signal and the RDS signal have the same bit rate. Upon turning on of the RDS receiver and/or switching over of the same to a transmitter receiving frequency different from that received so far, a control signal is generated which, upon occurrence of the next rising edge or, alternatively, of the next falling edge of the RDS signal, effects such a phase angle shift of the bit rate clock signal that the bit rate clock signal, starting from that occurrence, is in phase synchronism with the RDS signal.