Abstract: Prior to transmission, data bits are arranged into matrices having blocks sized in accordance with a size or rate of an error burst. The matrices are arranged into an ordered set having first and second dimensions. One or more sets of check bits are generated for each block of data bits. At least one set of first check bits relates to the first dimension, and at least one set of second check bits relates to said second dimension. The ordered set of matrices is transmitted across a transmission channel and received at a decoder-corrector. One or more errors in data bits of the ordered set of matrices are detected and corrected, by the decoder-corrector, based on the check bits.

Abstract: A communication system according to the present invention comprises a transmitter for performing low-density parity-check (LDPC) coding and a receiver for performing LDPC decoding based on the “Sum-Product algorithm”, and performing a synchronous control and a user detection by using a sum of absolute values of logarithm likelihood ratio of the posterior probability of each bit that is output as a decoding result.

Abstract: The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing circuit operation information that uses hardware description language and a library for performing a logic synthesis of the circuit operation information and converting to a net list; and a display unit. The information processor hierarchically arranges statement by statement the circuit operation information that is stored in the storage unit, and then refers to the library, performs a logic synthesis of the circuit operation information that has been hierarchically arranged and converts to a net list. The information processor then detects redundant fault sites, which are sites that are logically redundant from the net list, and displays information showing the redundant circuits that contain the redundant fault sites on the display unit.

Abstract: Disclosed are an apparatus and a method for reducing the coding complexity in an LDPC code used in a digital communication system. In the method, parameters required for coding are determined according to a coding rate and a code length, a seed matrix is generated according to values of the parameters, a plurality of cell matrices are generated according to the values of the parameters, a parity check matrix is generated using the seed matrix and the cell matrix, and information bits are coded from the parity check matrix. The method can be realized by a small memory and a simple shift register and can perform coding even without obtaining a generation matrix, thereby remarkably reducing the complexity of a system.

Abstract: A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

Abstract: A parallel precoder circuit executes a differential encoding operation on an n-row parallel input information series, and outputs an n-row parallel output information series, where 2?n. Output sets of differential encoding operation circuits each of which having a largest column number from among differential encoding operation circuits disposed in first row to (n?1)th row become first-row to (n?1)th-row parallel outputs information series, and an output set of an nth-row delay circuit becomes nth-row parallel output information series.

Abstract: A method of detecting two-dimensional codes using a plurality of light and dark data bits arranged two-dimensionally. The method includes detecting the code as a gray scale value image, splitting the detected gray scale value image into image areas corresponding to the individual data bits, determining a binarizing threshold representing a specific gray scale value for the image areas, carrying out a respective binarizing of the gray scale value of the individual image areas by means of a binarizing threshold to produce a bit sequence which represents the data bits and consists of the values 0 and 1, supplying the bit sequence to an error correction algorithm to recognize and/or correct bit errors within the bit sequence, identifying uncertain image areas whose gray scale values each lie close to the binarizing threshold, and taking the uncertain image areas into special account in the error correction.

Abstract: Disclosed are an error-detecting encoding apparatus for creating parity bits by error-detecting encoding processing, appending the parity bits to an input data string and encoding the data string, and an error-detecting decoding apparatus for detecting error using these parity bits. Data segmenting means segments an input data string, which is to undergo error-detecting encoding, into a plurality of sub-data strings, dividing means divides the segmented sub-data strings by a polynomial, which is for generating an error-detecting code, and calculates remainders, converting means applies conversion processing, which conforms to a segmentation position of the sub-data strings, to the remainders on a per-remainder basis, and combining means combines converted values, which have been obtained by the conversion processing, and outputs parity bits. An encoder appends this parity to a data string, and a decoder detects error using this parity.

Abstract: Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: Method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received, and combining the results of the calculating step and the generating step.

Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. At the end of a CRC error detection division operation, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: A method for decoding information received at a network device may include a first decoding process which applies a first algorithm iteratively until a stopping criterion is reached and a second decoding process which may flip a logic state of one or more bits. In one implementation using low density parity check (LDPC) codewords, bits may be flipped after evaluating check nodes having the lowest metrics and/or assessing the parity relationships of bit nodes and/or edges associated with those check nodes. Devices and systems for decoding are also disclosed as well as various other embodiments.

Abstract: A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The second stage SOVA detector comprises pipeline registers. The pipeline registers receive the relative state domain data outputs and the selection bit outputs and provide pipelined outputs. The second stage SOVA detector comprises a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.

Abstract: The present invention provides a system and method for storing re-synchronization, error correction and/or error detection data within an existing communication protocol, while still maintaining full compliance to a standard, such as the MPEG-2 AAC standard. By doing so, data information can still be passed from an encoder to a decoder via a channel using an existing and well known standard transport protocol. However, the existing well known transport protocol can now include the data necessary for synchronization of the decoder to the received raw data, along with error detection and error correction by the decoder.

Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. At the end of a CRC error detection division operation, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.

Abstract: Decoding LDPC (Low Density Parity Check) code with new operators based on min* operator. New approximate operators are provided that may be employed to assist in calculating one or a minimum value (or a maximum value) when decoding various coded signals. In the context of LDPC decoding that involves both bit node processing and check node processing, either of these new operators (i.e., the min† (min-dagger) operator or the min? (min-prime) operator) may be employed to perform the check node processing that involves updating the edge messages with respect to the check nodes. Either of these new operators, min† operator or min? operator, is shown herein to be a better approximate operator to the min** operator.

Abstract: A more convenient checksum writing method and checksum checking apparatus. The method includes: calculating a first checksum by reading values from the memory and summing the read values; calculating a first mode checksum by subtracting values written in a predetermined area of the memory from the first checksum; initializing a second checksum to be zero if the first mode checksum does not meet a predetermined condition; calculating a second mode checksum by inverting the second checksum and adding the inverted second checksum to the first mode checksum; and writing the inverted second checksum value in the predetermined area of the memory, if the second mode checksum is equal to the second checksum.

Abstract: A method for adapting the data rate in a communication apparatus as provided, wherein the individual data blocks in a data stream are punctured in accordance with a specific puncturing pattern for adaptation of the data rate, with the puncturing pattern being designed such that it is has a puncturing rate which increase continuously from a central region of the individual data blocks toward at one end of the individual data blocks.