Abstract: A system and method for automatically improving performance of a first graphical program that performs one or more repetitive operations, e.g., in a loop. The first graphical program may be programmatically analyzed and may be programmatically modified based on the analysis. Programmatically modifying the first graphical program may include programmatically modifying the one or more repetitive operations or the loop performed by the first graphical program, where the modification results in improved performance. In one embodiment, the performance of the first graphical program may be improved by increasing deterministic behavior. For example, deterministic behavior may be especially important for a real-time or time critical application. In one embodiment, determinism may be increased by removing functionality from the first graphical program which causes time latency problems.

Abstract: A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle.

Abstract: A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language (100) and identifying a loop construct within the language independent model (705). A determination can be made as to whether the loop construct is bounded (725). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences 735). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique (740, 755).

Abstract: Methods and apparatuses for dynamic type checking are described. For one embodiment runtime code generation is used to effect dynamic type checking by generating code specialized to different object types. For one embodiment a virtual dynamic type check (DTC) function is generated for each object at run time. The virtual DTC function contains a sequence of instructions to type check every element (type) within an object's type hierarchy. The virtual DTC function is tailored for a particular type and thus conducts dynamic type checking more efficiently for objects of the particular type. For one embodiment the DTC function can complete type checking of interface type hierarchies. For one embodiment a compiler may determine whether a type is a class type or interface type and may generate a virtual DTC function only for interface types.

Abstract: A method for selecting a basic block in a computer program comprising providing a computer program including an entry basic block and a plurality of basic blocks forming control flow paths, determining that immediate subsets of the control flow paths commencing with the entry basic block are essentially unbiased subsets, determining that the basic blocks in the immediate subsets of the flow control paths have essentially the same height, and selecting any one of the basic blocks in the immediate subsets of the flow control flow paths. The height may be a height selected from the group of heights consisting of resource height and dependence height. An article of manufacture including a computer-readable medium having instructions for selecting a basic block or for forming a new computer control flow path. A computer system comprising a computer program having instructions for selecting a basic block or for forming a new computer control flow path.

Abstract: A computer system includes an aggregator network that couples a plurality of processes on which an application executes to a debugger user interface. Using the debugger user interface, commands are created and sent through the aggregator network to the processes and messages from the processes are routed through the aggregator network to the debugger user interface. Whenever possible, the aggregator network combines the processors' messages into fewer messages and provides a reduced number of messages to the debugger user interface. The aggregated messages generally contain the same information as the messages they aggregate and identify the processes from which the messages originated. The aggregator network examines the processor messages for messages that have identical or similar data payloads and aggregates messages that have identical or similar payloads.

Abstract: One embodiment of the present invention provides a system that initializes system classes for a virtual machine during build time for the virtual machine, so that portions of the system classes can be stored in Read Only Memory (ROM). During virtual machine build time, the system loads system classes for the virtual machine. Next, the system identifies which of the system classes can be initialized at build time and then initializes the identified system classes. The system then stores portions of the system classes in a ROM image, so that the portions of the system classes can be accessed from the ROM image during subsequent run-time execution of the virtual machine. In this way, this embodiment of the present invention reduces the amount of time required to initialize system classes during run-time execution of the virtual machine.

Abstract: A first storage device stores a plurality of program codes. Each program code has an identifier. A second storage device has at least one storage area, which stores a program code to be executed of the plurality of program codes stored in the first storage device. A first variable storage area holds the identifier of the program code stored in the second storage device. A controller breaks execution of the program code when the contents of a command match those of the first variable storage area.

Abstract: The collating device includes the Formant estimation section that estimates feature amount data that represents a time-based change in frequencies of first and second Formants from voice data input through the microphone. The difference computing section calculates a difference between some reference feature amount data and the feature amount data as the feature-amount difference data. This feature-amount difference data is stored in a database. The feature-amount difference data corresponding to voice data input upon collation is collated with the feature-amount difference data registered in the database, and the result is output.

Abstract: A script generator facilitates the testing of software, such as application software or other software. The script generator automatically generates a script from metadata that includes code defining the application software. The script contains logic for the application software. The script is used in conjunction with a second set of data, such as a spreadsheet, that is extracted from application data and metadata by the script generator or is created manually. An execution engine uses the script and corresponding second set of data to simulate an end user's potential use of the application software. The application software is thus efficiently tested in this manner.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.