Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

Abstract: According to one embodiment, a magnetic device includes first and second conductive portions, first and second stacked bodies, and a controller. The first conductive portion includes first to third region. The third region is between the first and second regions. The first stacked body includes first and second magnetic layers. The second magnetic layer is between the third region and the first magnetic layer. The second conductive portion includes fourth to sixth regions. The sixth region is between the fourth and fifth regions. The second stacked body includes third and fourth magnetic layers. The fourth magnetic layer is between the sixth region and the third magnetic layer. The first stacked body is configured to be in a first low or high electrical resistance state. The second stacked body is configured to be in a second low high electrical resistance state.

Abstract: An electronic device, such as a memory device, may include various circuit components. The electronic device may also include one or more voltage testing circuits to determine whether signals of one or more of the circuit components are within acceptable voltage ranges of the respective circuit components. Systems and methods are described to improve correct voltage measurement of the received signals by a voltage testing circuit. In particular, multiple supply voltage levels are provided to different components of the voltage testing circuit to provide a sufficient headroom voltage gap between received signals and the supply voltages. For example, some active circuits (e.g., operational amplifiers) of the voltage testing circuit may receive a higher supply voltage of the electronic device compared to one or more other circuits of the voltage testing circuit.

Abstract: A neuromorphic device including: a plurality of unit weighting elements connected to a bit line in a manner that shares the bit line, each of the plurality of unit weighting elements being connected to a source line and comprising a fixed layer of which a magnetization direction is fixed, a free layer of which a magnetization direction changes in parallel with or in anti-parallel with the fixed layer, and a tunnel barrier layer arranged between the fixed layer and the free layer and a plurality of drive transistors being selectively turned on according to a plurality of bit selection signals, respectively, and correspondingly driving the unit weighting elements, respectively, wherein the plurality of unit weighting elements have different resistances in such a manner as to correspond to bits, respectively, of a synapse weight.

Abstract: A fuse circuit that permits a fuse to be selected and programmed using a single fuse pad. The fuse circuit includes a fuse pad to receive a first voltage, a fuse coupled in series with a voltage controlled switch between the fuse pad and a reference node, and a switch control circuit coupled in series between the fuse pad and the reference node and in parallel with the fuse and the voltage controlled switch, the switch control circuit being configured to select and program the fuse responsive to the first voltage received at the fuse pad. The fuse pad may subsequently be grounded and a sense circuit may be coupled to the fuse to measure a voltage dropped across the fuse to determine whether the fuse has been programmed.

Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.

Abstract: In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

Abstract: A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.

Abstract: Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.

Abstract: A memory system includes: a memory device suitable for providing row-hammer data to set refresh rates for adjacent word lines of a target word line, and performing a target refresh operation on one or more word lines corresponding to a first row-hammer address according to a first target refresh command; and a memory controller suitable for generating a plurality of sampling addresses by sampling an active address, generating a plurality of counting values by comparing the sampling addresses with the active address, calculating a plurality of adjacent addresses corresponding to the sampling addresses based on the counting values and the row-hammer data, and providing the adjacent addresses as the first row-hammer address with the first target refresh command.

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

Abstract: A circuit includes an operational amplifier including an inverting input terminal capacitively coupled to each of an OTP cell array and an NVM cell array and first and second output terminals, an ADC coupled to the first and second output terminals, thereby configured to receive a differential output voltage from the operational amplifier, and a comparator coupled to the ADC and configured to output a data bit responsive to a digital output signal received from the ADC. The circuit is configured to cause the operational amplifier to generate the differential output voltage based on each of a current received from an OTP cell of the OTP cell array and a voltage received from an NVM cell of the NVM cell array.

Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

Abstract: Transistor antifuses are disclosed. An apparatus may include an antifuse that may be configurable either as a short between a first node and a second node or as an open between the first node and the second node. The antifuse may include a selection transistor and an antifuse transistor. A source or drain of the selection transistor may be electrically coupled to the first node. A gate of the selection transistor may be configured to receive a selection voltage. A gate of the antifuse transistor may be electrically coupled the other of the source or drain of the selection transistor. A source or drain of the antifuse transistor may be electrically coupled to the second node. Associated devices, systems, and methods are also disclosed.

Abstract: A selective non-volatile memory device includes a first electrode, a second electrode and at least one layer made of an active material. The device has at least two programmable memory states associated with two voltage thresholds and also provides a selective role when it is in a highly resistive state.

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.