Patents Examined by Mursalin Bin Hafiz
  • Patent number: 7126220
    Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: October 24, 2006
    Assignee: NanoNexus, Inc.
    Inventors: Syamal Kumar Lahiri, Frank Swiatowiec, Fu Chiung Chong, Sammy Mok, Erh-Kong Chieh, Roman L. Milter, Joseph M. Haemer, Chang-Ming Lin, Yi-Hsing Chen, David Thanh Doan
  • Patent number: 7060540
    Abstract: A method of fabricating a thin film transistor array is provided. A first patterned conductive layer that distributes over an area range exceeding the designated display region is formed over a substrate. A first dielectric layer is formed over the substrate, wherein the first dielectric layer has the thickness getting smaller toward the edge, so that the first patterned conductive layer outside the designated display region is exposed. A second patterned conductive layer is formed over the first dielectric layer. The second patterned conductive layer and the exposed first patterned conductive layer are electrically connected. A second dielectric layer having a plurality of contact openings therein is formed over the substrate. A plurality of pixel electrodes is formed over the second dielectric layer such that the pixel electrode and the second patterned conductive layer are electrically connected through the contact openings. Finally, various layers outside the designated display regions are removed.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: June 13, 2006
    Assignee: Quanta Display Inc.
    Inventor: Meng-Yi Hung
  • Patent number: 7037817
    Abstract: A semiconductor device has a first semiconductor layer composed of a group III–V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III–V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: May 2, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Patent number: 7002233
    Abstract: An integrated circuit including a substrate, a conductive layer, at least one inductive element superposed on the conductive layer and formed by a metallic turn having an outer contour and an inner contour, which bound between them a surface referred to as the radiation surface, and insulating material for insulating the conductive layer from the inductive element. The conductive layer has a surface substantially identical to the radiation surface.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: February 21, 2006
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventors: Benoît Butaye, Patrice Gamand