Patents Examined by Mushifique Siddique
  • Architectures and layouts for an array of resistive random access memory cells and read and write methods thereof
    Patent number: 10755779
    Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 25, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • Programmable controller for controlling automatic machines, having CPU to received control with respect to own apparatus, when external storage is authenticated based on authentication information
    Patent number: 10496062
    Abstract: A programmable controller according to an embodiment includes a connection interface, a storage, and a controller. The connection interface can be connected with an external storage. The storage stores information for authentication. The controller accepts control for the programmable controller when the external storage is connected to the connection interface and the external storage is authenticated based on identification information stored in the external storage and the information for authentication.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: December 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eigo Fukai, Makoto Toko
  • Refresh in memory based on a set margin
    Patent number: 10147475
    Abstract: The present disclosure includes apparatuses and methods related to refresh in memory. An apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage. The reference voltage can be determined by the threshold voltage being within a set margin of a second state.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato