Abstract: A two-wire smart load control device, such as an electronic switch, for controlling the power delivered from a power source to an electrical load comprises a relay for conducting a load current through the load and an in-line power supply coupled in series with the relay for generating a supply voltage across a capacitor when the relay is conductive. The power supply controls when the capacitor charges asynchronously with respect to the frequency of the source. The capacitor conducts the load current for at least a portion of a line cycle of the source when the relay is conductive. The load control device also comprises a bidirectional semiconductor switch, which is controlled to minimize the inrush current conducted through the relay. The bidirectional semiconductor switch is rendered conductive in response to an over-current condition in the capacitor of the power supply, and the relay is rendered non-conductive in response to an over-temperature condition in the power supply.

Abstract: An apparatus includes a ping detection module that detects a ping signal transmitted from a secondary pad to a primary pad. The secondary pad is located on a mobile device and the primary pad located on a stationary WPT device, where the stationary WPT device transmits power through the primary pad to the secondary pad of the mobile device during a wireless power transfer operation. The ping signal includes a mobile device ID and the mobile device ID is unique to the mobile device. The apparatus includes an ID detection module that detects the mobile device ID from the ping signal received at the primary pad and a pairing module that pairs the stationary WPT device with the mobile device in response to detecting the mobile device ID of the mobile device.

Abstract: Systems and methods for adaptive modulation of MOSFET driver key parameters for improved voltage regulator efficiency and reliability in a voltage regulator may include a power stage. The power stage may include a high side switch including a high side gate, a peak voltage detection circuit, and a high side driver strength modulator circuit. The high side driver strength modulator circuit may determine a high side driver strength level. The high side driver strength modulator circuit may also connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level. The high side driver strength modulator circuit may also disconnect a remaining subset of the set of high side gate drivers from the high side gate.

Abstract: A flexible pet protective collar having stays formed of a more rigid material than flexible sheets of the collar, the stays being disposed inside channels located at seams of the collar.

Abstract: A latch with magnetically-assisted operation is described. In some embodiments, a latch may include: a first magnetic device fixedly coupled to a first portion of an Information Handling System (IHS); a second magnetic device coupled to a second movable portion of the IHS; and a carrier, comprising: a compression bracket fixedly coupled to the first portion of the IHS, the compression bracket having a slot configured to accommodate the second magnetic device, at least one guidepost configured to receive a return spring, and at least one stopping pin; and a actuator bracket movably coupled to compression bracket, the actuator bracket having a button configured to translate the second magnetic device with respect to the first magnetic device, at least one orifice configured to engage with the at least one guidepost, and at least one detent configured to engage with the at least one stopping pin.

Abstract: In a power converter, each gate-driving circuit uses charge from a selected pump capacitor operate a corresponding switch. The switches transitions between different states, each of which corresponds to a particular interconnection of pump capacitors. During clocked operations, the first switch closes, thereby establishing a connection with the first pump capacitor. Prior to the first switch closing, the second switch closes.

Abstract: The present disclosure provides for a computer chassis design, which includes a sled and a sliding bracket. The sliding bracket includes a removable power supplier socket on a first end and a sliding return lever on the second end. When the sled is removed from the computer chassis, the removable power supplier socket can move out of the chassis via a set of mechanisms. The set of mechanisms can include an elastic element to cause the power supplier socket to automatically rotate out of the chassis. The sled can be shaped to extend behind the power supplier socket.

Abstract: An electronic apparatus includes a magnetic sensor which acquires a status of a magnetic field around the electronic apparatus, an angular velocity sensor, and a processor. The processor controls whether the detection of an angular velocity of a spatial movement of the electronic apparatus is performed by the angular velocity sensor or a magnetic gyro sensor composed of the magnetic sensor, based on the status of the magnetic field acquired by the magnetic sensor.

Abstract: A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

Abstract: Disclosed are a wireless power transmitting apparatus and a method thereof. The wireless power transmitting apparatus wirelessly transmits power to a wireless power receiving apparatus. The wireless power transmitting apparatus detects a wireless power transmission state between the wireless power transmitting apparatus and the wireless power receiving apparatus, and generates a control signal to control transmit power based on the detected wireless power transmission state. The wireless power transmitting apparatus generates the transmit power by using first DC power based on the control signal, and transmits the transmit power to a transmission resonance coil through a transmission induction coil unit based on an electromagnetic induction scheme.

Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and dis-connection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Abstract: Improved systems, apparatus, methods, and programming useful for the automated analysis of complex compounds using mass spectrometers. Systems, apparatus, methods, and programming according to the invention provide for the automatic determination by a controller 54 of a mass spectrometer 14, 214 of an analysis operation to be implemented using the mass spectrometer, the analysis operation adapted specifically for analysis of one or more substances based contained within a compound based on identification of the compound and/or substances provided by a user of the spectrometer, and a database 66 or other library of information concerning suitable processes or process steps for analyzing substances.

Abstract: A buffer circuit includes a first MOSFET including a first source electrode, a first gate electrode, and a first drain electrode, and a second MOSFET, which includes a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, and the first gate electrode and the second gate electrode are electrically connected to each other.

Abstract: An apparatus includes a first charging coil with one or more conductors arranged in a first winding pattern, a second charging coil with one or more conductors arranged in a second winding pattern, and a ferrite structure with a main section with a top side, a first side section and a second side section. A portion of the top side of the main section is adjacent to a portion of the bottom side of the first side section and the second side section. A portion of the first and second charging coils are positioned adjacent to the top side of the main section interior in between the first and second side sections. A portion of the first charging coil is adjacent to the bottom of the first side section. A portion of the second charging coil is adjacent to the bottom of the second side section.

Abstract: Circuits for a voltage regulator are provided, comprising: an inductor having a first side coupled to an input voltage; a first flying capacitor; a second flying capacitor; and a plurality of switches, wherein: in a first state, the plurality of switches couple: a second side of the inductor to a second side of the first flying capacitor and an output node; a first side of the first flying capacitor to a first side of the second flying capacitor; and a second side of the second flying capacitor to a voltage supply, in a second state, the plurality of switches couple: the second side of the inductor to the first side of the second flying capacitor; the second side of the second flying capacitor to the output node and the first side of the first flying capacitor; and the second side of the first flying capacitor to the voltage supply.

Abstract: In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

Abstract: An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.