Patents Examined by N. Kelley
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Patent number: 5977575Abstract: The semiconductor image sensor device of the multiple chip mount type is constructed such that electrical and mechanical connections are carried out concurrently among chips. Coupling chips 4 are utilized to couple a plurality of semiconductor image sensor chips 1 with each other, and the couple one semiconductor image sensor chip 1 to a driver substrate 3 which mounts thereon a semiconductor driving chip 2 for driving the semiconductor image sensor chips 1.Type: GrantFiled: April 27, 1993Date of Patent: November 2, 1999Assignee: Seiko Instruments Inc.Inventors: Masaaki Mandai, Hitoshi Takeuchi, Yutaka Saito, Tomoyuki Yoshino
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Patent number: 5920125Abstract: Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.Type: GrantFiled: May 9, 1997Date of Patent: July 6, 1999Assignee: International Business Machines CorporationInventors: James Vernon Ellerson, Joseph Funari, Jack Arthur Varcoe
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Patent number: 5905290Abstract: A bi-stable logic device 110 comprises first and second inverters 112 and 114. A first resistive connection 140 is made between the input 134 of the first inverter 112 and the output B.sub.-- of the second inverter 114 and a second resistive connection 142 is made between the input 138 of the second inverter 114 and the output B of the first inverter 112. The first and said second resistive connections are also capacitively coupling. The device 110 is hardened from single event upset. Other systems and methods are also disclosed.Type: GrantFiled: August 2, 1993Date of Patent: May 18, 1999Assignee: Texas Instruments IncorporatedInventor: Theodore W. Houston
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Patent number: 5898220Abstract: A device and method for increasing integrated circuit density comprising a pair of superimposed dies with a plurality of leads extending between the dies. The device is produced by providing a lower die which has a plurality of bond pads on a face side of the lower die. A layer of dielectric or insulative shielding is applied over the lower die face side. Leads are applied to an upper surface of the shielding layer. A plurality of lower die bond wires is attached between the lower die bond pads and an upper surface of their respective leads. A second layer of dielectric or insulative shielding is applied over the leads and the portion of the lower die bond wires extending over the lead upper surfaces. A back side of the upper die is adhered to an upper surface of the second shielding layer. A plurality of upper die bond wires are attached between a plurality of bond pads on a face side of the upper die and the upper surface of their respective leads.Type: GrantFiled: August 14, 1997Date of Patent: April 27, 1999Assignee: Micron Technology, Inc.Inventor: Michael B. Ball
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Patent number: 5886362Abstract: An integrated circuit die is tested by inserting test probe needles into flat solder pads before reflow. The testing is performed at different temperatures to functionally test the integrated circuit die. The solder pads are flat during probe test to improve the uniform contact point and pressure for the test probes, and help avoid slippage or sliding. The probe needles may cause indentation in the solder pads. Following probe test, the solder pads are reflowed to transform the solder pads into solder bumps. Reflow after probe test removes any indentations from the solder pads created during the probe test and leaves only rounded solder bumps without probe damage. The solder bumps are used to flip-chip interconnect the IC into end user systems.Type: GrantFiled: December 3, 1993Date of Patent: March 23, 1999Assignee: Motorola, Inc.Inventors: Lavoie R. Millican, Vern H. Winchell, II
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Patent number: 5886404Abstract: A bottom lead semiconductor package includes a plurality of outer leads, wherein an outer portion of each of the outer leads is downwardly bent, and inner leads extend from a corresponding one of the outer leads respectively and are bent at least once upwardly and folded over onto a corresponding upper surface of the outer leads. A semiconductor chip is attached to an upper surface of each of the inner leads by a nonconductive adhesive, and a plurality of conductive wires or bumps electrically couples the chip to the inner leads. A molding compound seals a portion of the package including the chip, the inner leads and the wires, but externally exposes a downwardly bent portion of each of the outer leads.Type: GrantFiled: June 17, 1997Date of Patent: March 23, 1999Assignee: LG Semicon Co., Ltd.Inventor: Joong-Ha You
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Patent number: 5773880Abstract: A non-contact IC card comprising a circuit board (10), an electronic circuit (9) mounted on the circuit board (10) and having a plurality of functions, a package (14) sealing the electronic circuit (9), a plurality of testing wire conductors (8) disposed on the circuit board (10) and connected at one end to the electronic circuit (9) and exposed at the other end from the package (14) for individually testing the functions of the electronic circuit (9). Each of the other end of the testing wire conductors (8) comprises a testing pad (11) disposed on the circuit board (10). The non-contact IC card may comprise insulating means electrically insulating the other end of the testing wire conductors or the testing pads (11) from outside.The present invention also resides in methods for manufacturing and testing the same.Type: GrantFiled: July 28, 1993Date of Patent: June 30, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hisashi Ohno