Abstract: An illustrative embodiment includes a method for checkpointing and restarting an application executing at least in part on one or more central processing units coupled to one or more hardware accelerators. The method comprises checkpointing the application at least in part by: transferring checkpoint data of the application to the one or more hardware accelerators; performing distributed compression of the application checkpoint data at least in part using the one or more hardware accelerators; and writing the compressed application checkpoint data to a storage device. The method further comprises restarting the application at least in part by: reading the compressed application checkpoint data from the storage device; transferring the compressed checkpoint data to one or more hardware accelerators; and performing distributed decompression of the application checkpoint data at least in part using said one or more hardware accelerators.

Abstract: Method and apparatus for monitoring and reconstructing a software-defined PLC are provided. The method includes: upon monitoring a PLC fails, obtaining, by a soft guardian, an operating state of each physical core on each server in a server cluster, and an operating state of each micro kernel on the each physical core; determining a target micro kernel according to the operating state of each physical core on each server, and the operating state of each micro kernel on each physical core; and transmitting a reconstruction instruction to the target micro kernel to instruct the virtual PLC to be reconstructed on the target micro kernel.

Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.

Abstract: Described are devices, systems and techniques for implementing atomic memory objects in a multi-writer, multi-reader setting. In an embodiment, the devices, systems and techniques use maximum distance separable (MDS) codes, and may be specifically designed to optimize a total storage cost for a given fault-tolerance requirement. Also described is an embodiment to handle the case where some of the servers can return erroneous coded elements during a read operation.

Abstract: Systems and methods for predictive technology incident reduction are disclosed. In one embodiment, in an information processing apparatus comprising at least one computer processor, a method for predictive technology incident reduction may include: (1) receiving a change record for a proposed change to a computer application or a computer network infrastructure; (2) analyzing the potential change for an adverse potential cross impact with another computer application or a computer system; (3) predicting a probability of failure and an impact of the proposed change using a model; (4) in response to a low predicted probability of failure, or a high predicted probability of failure with a low predicted impact: approving the proposed change; and implementing the proposed change; and (5) in response to a high predicted probability of failure and a high predicted impact, rejecting the proposed change.

Abstract: Systems and methods for predicting computing system issues include: receiving a set of incident management tickets for a set of computing system issues and a set of computer log files for multiple modules of the computing system; arranging the set of tickets into chronologically ordered groups associated with particular computing system issues; pre-processing the set of computer log files to remove specified information, append to each log entry an indicator of the module of the log file, and merge the log entries; determining for each group a set of patterns for the group's associated computing system issue before the group's associated computing system issue arises; calculating for each pattern in each group a similarity score; selecting a subset of patterns whose similarity scores exceed a specified threshold; and generating a computing model associating the subset of patterns in each group with the group's associated computing system issue.

Abstract: A method is used in monitoring an application in a computing environment. The method represents execution of the application on a system as a finite state machine. The finite state machine depicts at least one state of the application, where the state indicates at least one of successful application execution and unsuccessful application execution. The method identifies an error state within the finite state machine, where the error state indicates the unsuccessful application execution. The method identifies, by analyzing the finite state machine, a non-error state as a cause of the unsuccessful application execution, where the unsuccessful application execution is represented as a path comprising a plurality of states, where the path comprises the non-error state. The method maps the non-error state to a location in the application to identify the cause of the unsuccessful application execution.

Abstract: A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.

Abstract: An accelerator manager monitors and logs performance of multiple accelerators, analyzes the logged performance, determines from the logged performance of a selected accelerator a desired programmable device for the selected accelerator, and specifies the desired programmable device to one or more accelerator developers. The accelerator manager can further analyze the logged performance of the accelerators, and generate from the analyzed logged performance an ordered list of test cases, ordered from fastest to slowest. A test case is selected, and when the estimated simulation time for the selected test case is less than the estimated synthesis time for the test case, the test case is simulated and run. When the estimated simulation time for the selected test case is greater than the estimated synthesis time for the text case, the selected test case is synthesized and run.

Abstract: A processing system, such as for an automobile, includes multiple processor cores, including an application core and a safety core, and a fault detection circuit in communication with the processor cores. The fault detection circuit includes a progress register for storing progress data of an application executed on the application core. The safety core, which executes a fault detection program, reads the progress data from the progress register, and generates an output based on the progress data and an expected behavior of the application. The safety core writes the output to a status register of the fault detection circuit. The fault detection circuit includes a controller that reads the status register and generates a fault signal when the output indicates there is a fault in the execution of the application. In response, the application core either recovers from the fault or runs in a safe mode.

Abstract: A processor includes a central processing unit (CPU) and diagnostic monitoring circuitry. The diagnostic monitoring circuitry is coupled to the CPU. The diagnostic monitoring circuitry includes a monitoring and cyclic redundancy check (CRC) computation unit. The monitoring and CRC computation unit is configured to detect execution of a diagnostic program by the CPU, and to compute a plurality of CRC values. Each of CRC values corresponds to processor values retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and peripheral subsystem while the CPU executes the diagnostic program.

Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.

Abstract: A memory system includes a memory device; and a controller configured to transmit a target address to the memory device for performing an access operation, receive from the memory device a reference address at which the access operation has been performed, and selectively re-perform the access operation based on the reference address. The controller re-performs the access operation when the reference address is different from the target address.

Abstract: Embodiments of the present disclosure relate to a system, a computer program product and a method for synchronizing data between a source disk and a target disk in a cluster by performing synchronization between a source disk and a target disk, the synchronization being performed while a plurality of application I/Os on a plurality of nodes in a cluster are configured to access the source disk; and wherein a coordinator and a plurality of workers in the cluster are configured to manage copying data from the source disk to the target disk.

Abstract: In one example a system includes a memory, and at least one memory controller to: detect a failed first memory location of the memory, remap the failed first location of the memory to a spare second location of the memory based on a pointer stored at the failed first memory location, and wear-level the memory. To wear-level the memory, the memory controller may copy data from the spare second location of the memory to a third location of the memory, and keep the pointer in the failed first memory location.

Abstract: A computer provides a secure, virtual personalized network (SVPN) for a first user with master privileges and at least a second user with guest privileges in the SVPN. Notably, the computer may execute a virtual machine that provides a container for the SVPN of the first user, and the first electronic device associated with the first user and a second electronic device associated with the second user may execute instances of an application that facilitates secure communication in the SVPN. Moreover, the first electronic device may store a set of first encryption keys and the second electronic device may store a set of second encryption keys, which allow the first electronic device and the second electronic device to securely communicate with each other via the SVPN. Note that the computer may not be able to access the set of first encryption keys or the set of second encryption keys.

Abstract: A method and apparatus for a mechanism of disaster recovery and instance refresh in an event recordation system are described. A first request for events associated with a first topic is received. A first set of events associated with the first topic are retrieved from a primary event recordation system. Each event from the first set of events includes a first commit identifier indicating the order with which each event is stored in the primary event recordation system. For each event from the first set of events a first replay identifier is determined based on the first commit identifier and a first value of a low commit identifier. The first replay identifier is exposed to event consumers for identifying the event. In response to the first request each event from the first set of events is transmitted with the replay identifier.

Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.

Abstract: A Deep Belief Network (DBN) feature extraction-based analogue circuit fault diagnosis method comprises the following steps: a time-domain response signal of a tested analogue circuit is acquired, where the acquired time-domain response signal is an output voltage signal of the tested analogue circuit; DBN-based feature extraction is performed on the acquired voltage signal, wherein learning rates of restricted Boltzmann machines in a DBN are optimized and acquired by virtue of a quantum-behaved particle swarm optimization (QPSO); a support vector machine (SVM)-based fault diagnosis model is constructed, wherein a penalty factor and a width factor of an SVM are optimized and acquired by virtue of the QPSO; and feature data of test data are input into the SVM-based fault diagnosis model, and a fault diagnosis result is output, where the feature data of the test data is generated by performing the DBN-based feature extraction on the test data.

Abstract: A memory device includes a memory region; and an access unit suitable for setting an offset value according to control of an external device, changing, in response to an access command of the external device for a first address of the memory region, the first address into a second address of the memory region based on the offset value, and performing an access operation for the second address.