Patents Examined by Nadine Norton
  • Patent number: 10144041
    Abstract: Use of supercritical CO2 for cleaning long, narrow pipes with a cross sectional area of less than 1000 square mm and a length of more than 500 meter. Cleaning is performed by adding a fluid to the lumen of the pipe (140); providing the fluid (2) in a supercritical state (6) inside the lumen; and subsequently, as a flushing step, while the fluid is in the supercritical state or in a liquid state, displacing the fluid (2) in the lumen of the pipe (140) and out of lumen of the pipe at a speed that causes a turbulent flow of the fluid, thereby flushing particles out of the lumen.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: December 4, 2018
    Assignee: Ocean Team Group A/S
    Inventors: Jens Peder Høg Thomsen, Søren Leth, Martin Mose Stenstrup
  • Patent number: 10037889
    Abstract: The present invention provides methods for chemical mechanical polishing (CMP polishing) spin coated organic polymer films on a semiconductor wafer or substrate as part of lithography or as part of electronic packaging. The methods comprising spin coating an organic polymer liquid on a semiconductor wafer or substrate; at least partially curing the spin coating to form an organic polymer film; and, CMP polishing the organic polymer film with a polishing pad and an aqueous CMP polishing composition having a pH ranging from 1.5 to 4.5 and comprising elongated, bent or nodular silica particles containing one or more cationic nitrogen or phosphorus atoms, from 0.005 to 0.5 wt. %, based on total CMP polishing composition solids, of a sulfate group containing C8 to C18 alkyl or alkenyl group surfactant, and a pH adjusting agent.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: July 31, 2018
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Julia Kozhukh, Lee Melbourne Cook, Michael E. Mills
  • Patent number: 10037893
    Abstract: A method and apparatus for etching a wafer are provided. The method includes placing a first wafer with a first target material into a first chamber, and placing a second wafer with a second target material into a second chamber. The second chamber is connected to the first chamber by a first pipe. The method also includes applying a first Xe-containing gaseous etchant into the first chamber to etch the first target material. A portion of the first Xe-containing gaseous etchant in the first chamber is unreacted during the etching of the first target material. The method further includes applying the unreacted portion of the first Xe-containing gaseous etchant from the first chamber into the second chamber through the first pipe to etch the second target material of the second wafer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu
  • Patent number: 10005100
    Abstract: A method of forming fine patterns includes the steps of forming a conductive layer on a base part, forming a sacrificial layer including an adhesive material on the conductive layer, the adhesive material including a catechol group, forming resist patterns on the sacrificial layer, and forming fine patterns by patterning the conductive layer using the resist patterns as a mask.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eun Ae Kwak, Min Hyuck Kang, Gug Rae Jo
  • Patent number: 9963662
    Abstract: An aqueous cleaning solution composition includes about 8.7 wt. % to about 10.7 wt. % sodium hydroxide and about 0.7 wt. % to about 1.1 wt. % of potassium sodium tartrate.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: May 8, 2018
    Assignee: Seacole-CRC, LLC
    Inventor: Benjamin K. Athneil
  • Patent number: 9966263
    Abstract: A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: May 8, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Ju Li, Li-Chieh Hsu, Yi-Han Liao, Chun-Tsen Lu, Chih-Hsun Lin, Hsin-Jung Liu
  • Patent number: 9958769
    Abstract: A plasmon generator including a wide portion and a narrow portion is manufactured by etching an initial plasmon generator using an etching mask. The etching mask includes a first mask layer for defining the shape of one of the narrow portion and the wide portion, and a second mask layer for defining the shape of the other of the narrow portion and the wide portion. The etching mask is formed by forming a first hard mask, a second initial mask layer and a second hard mask in this order on a first initial mask layer, and etching the first and second initial mask layers by using the first and second hard masks.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 1, 2018
    Assignee: HEADWAY TECHNOLOGIES, INC.
    Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Seiichiro Tomita, Shigeki Tanemura, Yukinori Ikegawa
  • Patent number: 9929021
    Abstract: A dry etching method provided to involve the steps of: (a) disposing a substrate within a chamber, the substrate having an amorphous carbon film; (b) preparing a plasma gas by converting a dry etching agent into a plasma, the dry etching agent containing at least oxygen and alkylsilane; and (c) conducting plasma etching on the amorphous carbon film by using the plasma gas and an inorganic film as a mask.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 27, 2018
    Assignee: Central Glass Company, Limited
    Inventors: Hiroyuki Oomori, Akifumi Yao
  • Patent number: 9921620
    Abstract: A method for manufacturing a housing of an electronic device includes the following steps. An area not to be etched is shielded and an etching area is exposed. The etching area is etched by photolithography and forming a plurality of heat dissipation holes of nanometer scale in the etching area. The area not to be etched is cleaned for removing the shielding.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: March 20, 2018
    Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Shyan-Juh Liu, Kar-Wai Hon, Sha-Sha Liu
  • Patent number: 9914853
    Abstract: Provided are a slurry composition to be used in chemical mechanical polishing (CMP), and a method for polishing a substrate. This slurry composition contains water, abrasive grains, and an alkylene polyalkylene oxide amine polymer having a solubility parameter in a range of 9-10. A preferred alkylene polyalkylene oxide amine polymer is given by general formula (1). (In general formula (1), m and n are positive integers, and A and R are alkylene oxide groups.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: March 13, 2018
    Assignee: Nihon Cabot Microelectronics K.K.
    Inventors: Tsuyoshi Masuda, Hiroshi Kitamura, Yoshiyuki Matsumura
  • Patent number: 9911622
    Abstract: Non-uniformity in a thickness of a silicon oxide film formed on a processing target object can be reduced even when an aspect ratio of an opening of a mask is increased. A silicon oxide film is formed by repeating a sequence including: (a) a first process of forming a reactant precursor on the processing target object by generating plasma of a first gas containing a silicon halide gas within a processing vessel of a plasma processing apparatus; (b) a second process of generating plasma of a rare gas within the processing vessel after the first process; (c) a third process of forming a silicon oxide film by generating plasma of a second gas containing an oxygen gas within the processing vessel after the second process; and (d) a fourth process of generating plasma of a rare gas within the processing vessel after the third process.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: March 6, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Tomoyuki Oishi, Masanobu Honda
  • Patent number: 9911611
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask (HM) mandrel along a first direction over a material layer, forming a first spacer along a sidewall of the HM mandrel, forming a second spacer along a sidewall of the first spacer and forming a patterned photoresist layer having a first line opening over the HM mandrel, the first spacer and the second spacer. First portions of the HM mandrel, the first spacer and the second spacer are exposed within the first line opening. The method also includes removing the first portion of the first spacer through the first line opening to expose a first portion of the material layer and etching the exposed first portion of the material layer to form a first opening in the material layer by using the exposed first portions of the HM mandrel and the second spacer as a sub-etch-mask.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Ru-Gun Liu, Chieh Chih Huang
  • Patent number: 9892969
    Abstract: A process of forming an electronic device includes providing a substrate having a major surface; etching a portion of a the substrate to define a trench extending from the major surface, wherein the portion of the trench has a first width, W1, along the major surface and a second width, W2, at a bottom of the portion of the trench, and wherein the first width is greater than the second width; depositing a protective layer along side surfaces of the portion of the trench; etching the substrate to extend a depth of the trench after depositing the protective layer; and removing the protective layer.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: February 13, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Takumi Horie
  • Patent number: 9892934
    Abstract: A method of removing a halogen includes performing a heating treatment on a halogen-containing film at a pressure higher than 1 atm and a temperature higher than 100 degrees C. in order to suppress a deterioration of the halogen-containing film while keeping an organic solvent, which is in a liquid phase and exhibits a polarity, in contact with a surface of the halogen-containing film.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: February 13, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Ryuichi Asako
  • Patent number: 9881806
    Abstract: A method of manufacturing a semiconductor device including a wafer using a plasma etching device which includes a chamber, a chuck provided in the chamber to dispose a wafer to be processed thereon, a focus ring disposed at a peripheral edge portion of the chuck, and a gas supplying mechanism configured to supply various types of gases depending a radial position of the wafer. The method includes: placing a wafer formed with an organic film on the chuck; introducing an etching gas which etches the organic film on the wafer from the process gas supplying mechanism to a central portion of the wafer; introducing an etching inhibiting factor gas having a property of reacting with the etching gas to the peripheral edge portion of the wafer from the gas supplying mechanism; and performing plasma etching on the wafer using the etching gas.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 30, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Katsunuma, Masanobu Honda, Kazuhiro Kubota, Hironobu Ichikawa
  • Patent number: 9881794
    Abstract: In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yi-Nien Su
  • Patent number: 9859165
    Abstract: A method for forming a semiconductor device structure is provided. The method includes receiving a structure having a first portion and a second portion, and a top surface of the first portion is higher than a top surface of the second portion. The method also includes forming a first material layer over the first portion and the second portion of the structure and forming a first material layer over the first portion and the second portion of the structure. The method further includes thinning the second material layer until the first material layer is exposed and removing a portion of the second material layer over the second portion of the structure to expose the first material layer thereunder. In addition, the method includes thinning the first material layer to expose the structure.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Chieh Wu, Hui-Chi Huang
  • Patent number: 9846357
    Abstract: According to one embodiment, a photomask manufacturing method for patterning a multilayer film into a mask pattern in the multilayer film is provided. The photomask manufacturing method includes preparing a substrate including the multilayer film provided on the substrate, obtaining an amount of position variation before and after the multilayer film is patterned if a position of the mask pattern is deviated before and after patterning the multilayer film, forming the mask pattern at a position deviated by the amount of the position variation from a target position, if the multilayer film is patterned and a pattern of the multilayer film is formed at the target position, and patterning the multilayer film with the mask pattern.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kosuke Takai
  • Patent number: 9837304
    Abstract: Method of manufacturing a semiconductor device is described that uses sidewall protection of a recessed feature to prevent loss of critical dimension during a cleaning process to remove etch residue. According to one embodiment, the method includes providing a substrate containing a film thereon having a recessed feature with a sidewall and a bottom portion, depositing a conformal film on the sidewall and on the bottom portion, removing the conformal film from the bottom portion in an anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall, and performing a cleaning process that removes etch residue from the recessed feature without etching the protection film or the sidewall.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 5, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Patent number: 9824893
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 21, 2017
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk