Abstract: A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

Abstract: A field-effect transistor includes a semiconductor layer (14) having a portion functioning as a channel region. The semiconductor layer (14) includes, as its constituent components, a plurality of electrically conductive microparticles (52), organic semiconductor molecules (53) bonded to the microparticles (52) so as to link the microparticles to one another (52), and cyclic molecules. Each of the organic semiconductor molecules (53) includes a ?-electron conjugated chain as its main chain, and the ?-electron conjugated chain is insulated by cyclic molecules.

Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Abstract: A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers.

Abstract: There is provided a nitride semiconductor light emitting device. A nitride semiconductor light emitting device according to an aspect of the invention may include: an n-type nitride semiconductor layer provided on a substrate; an active layer provided on the n-type nitride semiconductor layer, and including quantum barrier layers and quantum well layers; and a p-type nitride semiconductor layer provided on the active layer, wherein each of the quantum barrier layers includes a plurality of InxGa(1-x)N layers (0<x<1) and at least one AlyGa(1-y)N layer (0?y<1), and the AlyGa(1-y)N layer is stacked between the InxGa(1-x)N layers.

Abstract: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.

Abstract: A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.

Abstract: A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.

Abstract: An image sensor includes a logic region and an APS region having a first gate electrode, a photo-detector, a first protecting layer, first spacers, and a second protecting layer. The first gate electrode is formed over a semiconductor substrate. The photo-detector is formed to a side of the first gate electrode within the semiconductor substrate. The first protecting layer is formed over the first gate electrode and the photo-detector. The first spacers are formed over the first protecting layer to the sides of the first gate electrode. The second protecting layer is formed over the first protecting layer and the spacers. The first and second protecting layers are for preventing a contaminant from reaching the photo-detector.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device comprises a semiconductor die including a bond pad, a redistribution layer, and a solder ball. The redistribution layer is formed by sequentially plating copper and nickel, sequentially plating nickel and copper, or sequentially plating copper, nickel, and copper. The redistribution layer includes a nickel layer in order to prevent a crack from occurring in a copper layer. Further, a projection is formed in an area of the redistribution layer or a dielectric layer to which the solder ball is welded and corresponds, so that an area of the redistribution layer to which the solder ball is welded increases, thereby increasing bonding power between the solder ball and the redistribution layer.

Abstract: Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.

Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

Abstract: A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.

Abstract: An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer.

Abstract: A high power light emitting diode, The high power light emitting diode comprises a light emitting diode chip, a main module, two first electrode pins, two second electrode pins, and at least one heat dissipation board. The main module has a concave and the light emitting diode chip is positioned in the concave. The first electrode pins are connected to a first side of the main module and also electrically connected to the light emitting diode chip. The second electrode pins are arranged on a second side of the main module that is relative to the first electrode pins wherein the second electrode pins and the first electrode pins are electrically opposite. The second electrode pins are electrically connected to the light emitting diode chip. The heat dissipation board is connected to a part of the main module between the first electrode pin and the second electrode pin.

Abstract: An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the source region with a channel (5) therefrom, —an active gate (8) overlying the channel and insulated from the channel by a first dielectric material (9) forming the gate oxide of the IGFET device, —a dummy gate (10) positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.