Abstract: In entropy, e.g. arithmetic, encoding and decoding, probability estimates are needed of symbols to be encoded and subsequently decoded. More accurate probability estimates are obtained by controllably adjusting the adaptation rate of an adaptive probability estimator. The adaptation rate is optimized by matching it to the actual probability values being estimated. In particular, the adaptation rate is optimized to be proportional to the inverse of the smallest value probability being estimated. Consequently, if the probability values being estimated are not small a "fast" adaption rate is realized and if the probability values being estimated are small a necessarily slower adaptation rate is realized.

Abstract: A decoding apparatus comprises detecting circuit for detecting a leading edge of a request signal which requests transmission of sequential data as digital signal, clock generator for generating a clock signal in response to an output signal from detecting circuits, and decoding circuit for decoding sequential data in accordance with the clock signal.

Abstract: An absolute encoder for detecting the absolute (as opposed to the relative) rotational displacement of an encoder shaft includes a pair of pitch signals recorded on tracks and an associated signal processing circuit. The pair of pitch signals have different periods (wave lengths) which are such that they have no common factors. The signal processing circuit includes magnetic sensors for producing absolute position data indicative of the degree of displacement of the encoder shaft, on the basis of the pitch signals. Through the use of a pair of pitch signals having periods with no common factor, a high degree of resolution is obtained, without having no significantly increase the number of pitch signal tracks.

Abstract: In a thermal printer, a driving apparatus moves a thermal head both longitudinally of and perpendicularly toward and away from a platen. A racing or idle rotating of gears is utilized in a driving mechanism for reciprocatingly moving a carriage carrying the head. Further, sector gears are used in a loading mechanism for moving the head toward and away from the platen. By combining these two unique structures, the rotational force of a drive motor is converted into the driving force to move the head toward and away from the platen when the carriage is switched between its forward movement and its backward movement. The result is that the carriage driving mechanism and the head load mechanism are operated by the common drive motor.

Abstract: The invention relates to a phase-locked loop comprising a phase detector (PD), an analog-to-digital converter (ADC), a loop filter (LF), a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). The phase jitter that occurs in such a hybrid phase-locked loop is reduced without enhancing the requirements as to the resolution of the digital-to-analog converter (DAC), in that a fractionizer (FR) is inserted after the loop filter (LF) that is operating at a first clock (TL), which fractionizer produces a main value (HW) and a residual value (RW), and the sum (SW) of the main value (HW) and a correction bit (KB) derived from the residual value (RW) is applied to the digital-to-analog converter (DAC) that is operating at a second clock (TA).

Abstract: An asynchronous serial data receiver for receiving a stream of data bits, characterized by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognizing points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading. The invention provides a high speed serial receiver which is particularly suitable for use within disc drives and data storage and retrieval systems in general. The serial data receiver of the present invention does not require a clock synchronized with the incoming data.

Abstract: A switched-capacitor sigma-delta modulator includes at least one memory element, at least one comparator, and at least one integrator. The at least one integrator has an input stage including a series circuit of a first switch, a first capacitor and a second switch, a third switch for connecting one of the two terminals of the first capacitor to ground potential, and a fourth switch for connecting the other of the two terminals of the first capacitor to ground potential. A nodal point is connected between the second and fourth switches and the other of the two terminals of the first capacitor. A negative feedback stage includes second and third capacitors each having one terminal connected to the nodal point. A fifth switch connects the other terminal of the second capacitor to a first potential. A sixth switch connects the other terminal of the third capacitor to a second potential. Seventh and eighth series-connected switches connect the other terminal of the second capacitor to the second potential.

Abstract: An input analog signal having a prescribed component is coverted into an n bit digital signal using low resolution circuitry. An m>n bit digial signal representative of the prescribed component is generated from stored information and past samples of the digital output signal and transformed into a coarsely quanitized analog signal. The prescribed component representative analog signal is subtracted from the input analog signal to form a difference representative signal which is converted into an n-m bit digital signal and them bit digital signal is combined with the n-m bit difference representative signal to produce an n bit digtial signal corresponding to the input analog signal.

Abstract: An information processor receives a residue number as an input and generates a mixed base number correspopnding to the residue number and a redundant residue digit corresponding to the residue number. The information processor includes a plurality of optical arithmetic and logic units (OALUs) arranged in channels and stages. Each digit of the residue number corresponds to a channel. Each channel produces a mixed base digit associated with the residue input number. The stages are serially arranged to successively generate mixed base digits corresponding to the residue number by performing modular multiplication and modular subtraction. Delay circuits are arranged parallel to the plurality of OALUs such that all of the mixed base digits are transmitted from the information processor at the same time. An additional channel of OALUs calculates the redundant residue digit based on the mixed base digits.

Abstract: A D/A converter utilizing a redundant binary expression includes a current supplying circuit and a current decreasing circuit operating responsive to each bit in the signal expressed in the redundant binary expression. The current supply circuit and the current decreasing circuit have their outputs connected together while their current driving capacities are established in response to the functions of the powers of 2 for each bit. In this manner, this D/A converter is able to convert the data signals expressed in the binary redundant expression directly into analog signals.