Abstract: An output load drive circuit including circuitry for adjusting a drive circuit bias current during operation in order to control driver circuit stability. The driver further includes circuitry which is self adjusting in response to ambient temperature fluctuations to control the overall gain of the driver.

Abstract: A circuit for synchronizing data pulses, comprises a D-type flip-flop and a set-reset type flip-flop. The D-type flip-flop is enabled by a system clock pulse train wherein the D-type flip flop conducts to product an output at a time controlled by the system clock pulse train if a data pulse is present, thereby synchronizing the data pulse with the system clock. The set-reset flip-flop is enabled by a second clock pulse train which lags after the system clock pulse train. The lag period is long enough to suppress transient conditions counsel by the leading edges of the system clock pulses. The set-reset flip-flop drives the D-type flip-flop.

Abstract: Comparator means comprising a pair of comparators connected to a logic gate and bistable circuit, said comparators are connected in anti-phase with a common input and separate outputs the separate outputs are combined by the logic gate to produce a single switching signal which is used to trigger the bistable to produce an output signal.

Abstract: A Schmitt trigger having first and second complementary switches is biased to exhibit hysteresis, switching at a high threshold level when the input signal increases, and switching at a low threshold level when the input decreases. The source driver for the Schmitt trigger is coupled to the input of at least one of the complementary switches by transition circuitry, such that the signal level representing one binary value is shifted closer to the level of the power supply voltage corresponding to such binary value without changing the logical value of the signal from the source driver. In one embodiment, the first inverter is a MOS transistor, the threshold level of which is set by a bias voltage applied to the gate of another MOS transistor. The second inverter is a pair of complementary CMOS transistors. In another embodiment, the first inverter also comprises a pair of complementary CMOS transistors. The threshold level is set by selecting the W/L ratio of the CMOS transistors of the first inverter.

Abstract: A method and apparatus of measuring the pulse width of electronic pulses which may have a large variation in amplitude. An electronic pulse includes a rising edge, a top and a falling edge and the method and apparatus measures a first point adjacent to the beginning of the rising edge, and measures a second point adjacent the beginning of the falling edge and measures the pulse width as the difference between the first and second points whereby the pulse width measurement is insensitive to the amplitude of the pulse width.

Abstract: A flip-flop (40) for a divide-by-2 frequency divider having a first stage (50) formed by two master-slave-type memory elements (10a, 10b) each having a two-input NOR gate (20a, 20b), and by a second stage (60) with 2 NOR gates (61, 62) connected as an RS flip-flop. The memory elements (10a, 10b) also include an enhancement-type MESFET transistor (30a, 30b), the gates (Ga, Gb) and the drains (Da, Db) of said transistors (30a, 30b) being coupled to the respective inputs of the NOR-gates (20a, 20b).

Abstract: A voltage sharing circuit which allows use of low voltage semiconductor devices to obtain higher output voltages is made up of a series stack of the low voltage devices with diode limiters provided to bias the low voltage devices such that the maximum voltage across any one of the low voltage devices is limited to a predetermined value.

Abstract: Switching power supply for generating a voltage for a pulsating load (2), in particular for generating a helix voltage for a TWT. The switching power supply is provided with a dc voltage source (1), a buffer (12) from which the load (2) is powered, and switches (3) and a control circuit (5) for regulating the charging of the buffer from the dc voltage source (1), whereby the power supply is provided with a circuit coupled to the dc voltage source (1), which circuit consists of a current source (6), the above-mentioned switches (3) and a primary (9) of a converter (7). The buffer (12) is powered from the secondary (11) of the said converter (7). The control circuit (5) controls the switches (3) by means of a signal which is a function of the rhythm of the pulsating load and the voltage across the buffer.

Abstract: A digital delay circuit that can be readily implemented in an integrated circuit is disclosed. The circuit includes a reference clock and two or more arrays of controlled delay elements. The reference clock is passed through one array of delay elements and the thus-delayed clock is compared to an undelayed clock in a phase detector or comparator the output of which is a control voltage. The latter is applied to the control inputs of each of the delay elements. The controlled delay elements may be in the form of buffers in which the delay is varible and controlled by the level of the control input.

Abstract: A pre-drive circuit performs on/off control of a switching transistor element (Q.sub.1) through a pulse transformer (T) having two primary windings (P.sub.1, P.sub.2). Switching elements (Q.sub.2, Q.sub.3) are respectively connected to the primary windings. Feedback circuits (D.sub.1, D.sub.2) connect signal output terminals of the respective switching elements (Q.sub.2, Q.sub.3) to control terminals of the opposite switching elements (Q.sub.3, Q.sub.2).

Abstract: A gate control circuit for a power MOS transistor (1), the first main electrode (D) of which is connected to a high voltage (V.sub.CC) through a load (L), the second main electrode (S) of which is grounded and the gate (G) of which is connected, during the switching ON period, to a low voltage source (V.sub.DD), comprises a switch (S1) for connecting at the switching ON of the power MOS transistor its first main electrode to its gate.

Abstract: A non-saturating voltage output driver circuit. A controlling mechanism is connected to a current source, a reference voltage and a load. A pre-driver is also connected to the current source. Connected to the controlling mechanism, the pre-driver and the load is a down-level output driver, the output of which is dependent on the reference voltage, but kept out of saturation and substantially constant over a temperature range.

Abstract: A pulse width modulator is provided with circuitry to eliminate high frequency noise spikes in its output. This circuitry is effective to slow down the switching time of the MOSFET switching transistor, increase the rise time of the voltage across the catch diode and improve the high frequency characteristics of the output filter. These benefits are achieved by only a few number of components.

Abstract: A transistor arrangement, particularly for the fast switching of inductive loads, includes a driving first transistor and a power output second transistor (T1, T2) interconnected as a Darlington pair having a base terminal, an emitter terminal and a collector terminal. A third transistor (T3) has its collector connected to the base of the first transistor (T1) and its emitter connected to the emitter terminal (E). A fourth transistor (T4) of a conductivity type opposite to that of the first, second and third transistors has its base connected to the collector terminal, its emitter connected to the base terminal, and its collector connected to the base of the third transistor (T3). This structure is particularly suited for a monolithic integration.

Abstract: A MOS differential to single ended converter circuit is provided for supplying a single ouput signal in response to first and second differentially related current being supplied to first and second junctions thereof. The converter circuit includes first and second MOS transistors each having gate, drain and source electrodes with the gate electrodes being coupled together while the drain and gate electrodes of the first transistor are interconnected. The drain and source electrodes of the pair of transistors are respectively coupled in series with the first and second junctions. First and second bipolar transistors each having first, second and control electrodes are provided for limiting the voltage swing at the drain of the second MOS transistor.

Abstract: A PIN diode switch suitable for switching radio-frequency voltages has a series circuit of two oppositely polarized PIN diodes, with a control current supplied to the junction between the two PIN diodes through the collector-emitter path of a transistor and through an inductor. The necessity of using a high-voltage power pack to generate a high reverse bias in order to avoid limiting the amplitude of the radio frequency voltage to be switched is not necessary, as in conventional PIN diode switches.

Abstract: A pulse width distortion correction circuit in which a digital input signal has its leading and trailing edges smoothed, is added to an analog pulse width control signal and compared to a reference voltage to provide a digital output signal with a corrected duty ratio. A duty ratio detection circuit detects the duty ratio of the digital output signal and provides the corresponding pulse width control signal so as to cause the duty ratio to assume a value of 50%.

Abstract: A dual current source MOSFET turn-on/off circuit includes a high gain PNP transistor as a turn-off current source and a high gain NPN transistor as a turn-on current source for a P-channel MOSFET. A switch in the base circuit of the NPN transistor turns on the NPN transistor current source which overpowers the PNP transistor current source. The net current charges the MOSFET gate-to-source capacitance which, upon reaching a threshold voltage, turns the MOSFET on. When the switch is opened, the PNP transistor current source discharges the gate-to-source capacitance, turning off the MOSFET. The circuit provides almost constant power dissipation independent of input voltage and a constant turn-on/off time independent of input voltage.

Abstract: A transfer circuit for signal lines comprises a bipolar transistor and two MIS transistors. A base of the bipolar transistor is connected to a first line of the signal lines, a collector of the bipolar transistor is connected to a power source, the two MIS transistors are connected in series, the connected point is connected to an emitter of the bipolar transistor, and one end of the series-connected MIS transistors is connected to the first line and the other end is connected to a second line of the signal lines. When the first line is transferred to the second line, the MIS transistor connected between the base and emitter of the bipolar transistor is made non-conductive and the other MIS transistor connected to the second line is made conductive. The transfer circuit constituted as above can carry out the transfer of the signal lines at a high speed by rapidly charging the second line.

Abstract: A power booster circuit is described. The booster circuit having amplifying circuitry comprises an input circuit, a switching circuit, and an auxiliary power circuit. The booster circuit is initiated by receipt of a signal by the input circuit. The amplifying circuit latches on when initiated by the switching circuit. The amplifying circuit produces a constant boosted power signal, using an auxiliary power circuit.