Abstract: Systems and methods are provided for performing the required phase calculation in a telecommunications system in order to optimize system performance more quickly and with reduced complexity as compared to prior approaches to solving this problem. In accordance with the preferred exemplary embodiment of the present invention, the phase delay of the precursor equalizer (EQ) is calculated off-line and as a result it is not necessary to fill the precursor EQ delay line with the indicated number of symbols as in the previous approach. Additionally, because the precursor EQ is fractionally spaced, both sine and cosine values of the 4kHz tone's initial phase can be achieved simultaneously. As a result, only 36 quick timing sequence (QTS) symbols are needed in order to perform the required estimation.

Abstract: A digital delay lock loop (DLL) circuit for receiving parallel data and clock signals, deserializing the high speed parallel data to low speed data, and for improving setup and hold times. A DLL circuit for an N-bit datapath, includes a clock DLL configured to provide a clock signal pulse within an eye opening of each of N data signals. The DLL circuit further includes N data DLLs, each being configured to adjust a delay of a data signal to substantially center the eye opening of the data signal on the clock signal pulse.

Abstract: A three-order sigma-delta modulator having a feedback and a feedforward configuration. The three-order sigma-delta modulator includes: an analog-to-digital converter; a digital-to-analog converter; a first integrating network; a second integrating network connected in series to the first integrating network; a third integrating network connected in series to the second integrating network; and an adder, to combine a feedforward gain signal generated by passing the first output signal from the first integrating network through a feedforward gain unit with a modulation signal that is generated by passing the third output signal from the third integrating network through a modulation gain unit and to generate a desired noise transfer function.

Abstract: A wireless communication apparatus includes an antenna receiving a radio signal, a variable gain amplifier amplifying the received signal using a variable gain, an analog-to-digital converter converting the amplified signal into a digital signal, a gain setting unit periodically updating the gain of the variable gain amplifier in accordance with an output from the analog-to-digital converter, and an operating mode selection unit selecting one of a plurality of operating modes characterized by different gain updating periods in accordance with the output from the analog-to-digital converter, the selected operating mode being set in the gain setting unit. With this construction, the precision in conversion by the analog-to-digital converter is maintained at a proper level when an environment for signal reception varies.

Abstract: A modulator phase shift keying modulator for performing data modulation by using the phase difference of each I/Q channel, comprising a data shifter for controlling delay of I/Q channel digital data at input terminals of the I/Q channels.

Abstract: If a phase difference between a synchronizing source signal F1 and a comparison signal F2 is higher than a first lower limit a or lower than a first upper limit b, a comparator 3 selects this phase difference, if the phase difference is not higher than the lower limit a, selects the lower limit a, and if the phase difference is not lower than the upper limit b, selects the upper limit b, and a divider 7A outputs a comparison signal F2 obtained by dividing a frequency of an output signal F0, to change a phase of the signal F2 so that if the phase difference is not higher than a second lower limit e lower than the lower limit a, the phase difference may become the lower limit a and, if the phase difference is higher than a second upper limit f higher than the upper limit b, the phase difference may become the upper limit b.

Abstract: A digital signal detector arrangement comprises at least two selectable baseband filters for receiving a digital signal, a signal estimator receiving the output signal of the selected baseband filter, a modulator unit receiving the estimated signal from the signal estimator, a subtractor for subtracting the modulated signal from the received digital signal, and a determination unit receiving the signal from the subtractor for selecting the baseband filter.

Abstract: A receiver configured to receive a plurality of signals k (k=1, 2, . . . , M) allocated in a first frequency band. The receiver includes a frequency conversion section for reallocating the signals k in a second frequency band for sampling by a single AD converter at a sampling frequency fs such that digital data of the sampled signals k are obtained in a third frequency band extending from zero Hz to a frequency represented by fs/2; and a signal extraction section for extracting a target base band signal k from the digital data obtained by the AD conversion section. The frequency conversion section performs the reallocation in such a manner that at least a frequency represented by Jfs/2 (J is an integer) is located between the frequencies of at least two of the signals k and that the sampled signals do not overlap.

Abstract: An apparatus and method is disclosed for avoiding metastability problems during a data transfer between a first circuit operating at first clock frequency and a second circuit operating at a second clock frequency. The first circuit sends an asynchronous control signal to the second circuit. The second circuit samples the asynchronous control signal at least two times and uses at least two samples of the asynchronous control signal to synchronize communication between the first and second circuits. The data is transferred between the first and second circuits when the circuits are synchronized. The second circuit indicates to the first circuit when the data transfer has been completed.