Abstract: A laminate package structure for a semiconductor device having a high resistance to humidity, reliability and electrical performance. A polyimide layer and copper foil patterns are formed on a metal base in the form of metal sheet. The metal base comprises a ground pattern maintained at the ground potential, and a plurality of land patterns on which solder balls are formed. The copper foil pattern comprises an island pattern on which an LSI chip is mounted, and an internal wiring patterns connected to electrodes of the LSI chip. The metal base pattern and the internal wiring patterns are electrically interconnected through via-plugs formed in through-holes by an electrolytic plating. A cap is adhesively bonded to the laminated metal base or one of the metal foil patterns.