Patents Examined by Nathan Kip Kelley
  • Patent number: 5635748
    Abstract: A NAND ROM with an improved integration level is described. A number of trenches are formed in stripe pattern at the surface of a semiconductor substrate, and an insulating film for isolation between devices is formed at the sidewalls, respectively, of each trench. A first unit array consisting of MOSFETs connected in series is arranged in each first active region defined between two adjacent trenches. A second active region is defined in the bottom of each trench and a second unit array is arranged therein. Distinguished from the trench isolation technique which provides trenches between unit arrays, instead, according to the present invention, sidewalls of insulating film are formed. The trench width is limited to the minimum feature size involving the lithography. On the other hand, the width of the insulating-film sidewalls are independent of the limitation, permitting the size of the 64-Mbit mask ROM chip to be about 2 mm smaller.
    Type: Grant
    Filed: January 10, 1995
    Date of Patent: June 3, 1997
    Assignee: NEC Corporation
    Inventor: Teiichiro Nishizaka
  • Patent number: 5514883
    Abstract: A field effect transistor is disclosed. The field effect transistor includes: a semiconductor substrate having at least an upper face; a semiconductor layered structure, formed on the upper face of the semiconductor substrate, the semiconductor layered structure including a channel layer; a source electric formed on the semiconductor layered structure; a drain electrode formed on the semiconductor layered structure at a position apart from the source electrode in a first direction by a prescribed distance; and a gate electrode, formed on the semiconductor layered structure between the source electrode and the drain electrode.
    Type: Grant
    Filed: January 6, 1995
    Date of Patent: May 7, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadayoshi Nakatsuka, Kaoru Inoue, Hiromasa Fujimoto, Hideki Yagita
  • Patent number: 5485038
    Abstract: A High-Density-Multi-Chip (HDMI) substrate structure (10) includes alternating conductor metallization (24,28,36,54,56) and insulating dielectric layers (14,38). The dielectric layers (14,38) are formed by curtain coating of ultraviolet photoimageable epoxy material, and the metallization (24,28,36,54,56) is formed by electroless plating or sputtering of copper. The dielectric layers (14,38) are photoimaged and developed to form via holes (16,40,44), and vias (18,42,46) are formed in the holes (16,40,44) by electroless copper plating. The metallization (24,28,36,54,56) can be formed in the same manner as the dielectric layers (14,38), or can alternatively be formed by subtractive photolithography using photoresist masks.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: January 16, 1996
    Assignee: Hughes Aircraft Company
    Inventors: James J. Licari, Deborah J. Smith
  • Patent number: 5468975
    Abstract: An optoelectronic semiconductor device includes a first cladding layer (1) of the first conductivity type provided on a substrate (11), an active layer (2), a second cladding layer (3) of a second conductivity type, an intermediate layer (4), and a third cladding layer (5) also of the second conductivity type, the thickness of the second cladding layer (3) being such that the intermediate layer (4) lies within the optical field profile of the active layer (2), while the intermediate layer (4) includes a semiconductor material with a lower bandgap than the second (3) and third (5) cladding layers. Such devices, often in the form of diode lasers, are used inter alia in optical glass fibre communication and optical disc systems. A disadvantage of such devices is that their starting currents are comparatively high.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: November 21, 1995
    Assignee: U.S. Philips Corporation
    Inventor: Adriaan Valster
  • Patent number: 5466972
    Abstract: Multilayer circuit devices include a plurality of metallized patterns thereon, said patterns being separated by a polymeric dielectric film. The various metallized patterns are interconnected by means of microvias through the polymeric film or films. Each of the metallizations is a composite including in succession from the substrate or from the polymeric film, a layer of titanium (Ti), a layer of titanium and palladium alloy (Ti/Pd), a layer of copper (Cu), and a layer of titanium and palladium alloy (Ti/Pd). The Ti--Ti/Pd--Cu--Ti/Pd composite is hereinafter referred to as TCT. The adhesion between the polymeric film and the top Ti/Pd layer is better than that between the polymer and gold (Au) and comparable to that between the polymer and an adhesion promoted Au layer. Use of the TCT metallization also results in additional cost reduction due to the elimination of Ni and Au layers on top of the Cu layer.
    Type: Grant
    Filed: May 9, 1994
    Date of Patent: November 14, 1995
    Assignee: AT&T Corp.
    Inventors: Aaron L. Frank, Ajibola O. Ibidunni, Douglas B. Johnson, Dennis L. Krause, Trac Nguyen
  • Patent number: 5461254
    Abstract: There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: October 24, 1995
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Lih-Shyng Tsai, Jiunn-Jyi Lin, Kwang-Ming Lin, Shu-Lan Ying
  • Patent number: 5461251
    Abstract: A symmetrical, SRAM silicon device comprises a substrate comprising a semiconductor material with, a set of buried local interconnection lines in the silicon substrate. A word line is located centrally on the surface of the device. Pull down transistors are located symmetrically one either side of the word line. Interconnections are formed in the same layer as a BN+ diffusion. There is only one wordline composed of polysilicon. The pull down transistors are located on opposite sides of the word line. The cell size is small. There is no layout, and the metal rule is loose. Pass transistor source and drain regions are formed in the substrate juxtaposed with the buried local interconnection line. There is a layer of gate oxide above the source region and the drain region, and a gate above the gate oxide juxtaposed with the source region and drain region.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: October 24, 1995
    Assignee: United Microelectronics Corporation
    Inventors: Ming-Tzong Yang, Chen-Chiu Hsue
  • Patent number: 5459341
    Abstract: A surface region of a P-type semiconductor substrate is defined by an isolation into plural active regions at which a semiconductor element is to be formed. A first diffusion region such as a drain region, a second diffusion region such as a source region, and a wiring member such as a word line are arranged at each active region. The surface of the word line is covered with a first insulating layer. A second insulating layer is provided, in which a region including in common each overhead region on at least two second diffusion regions is removed, leaving an overhead region on the first diffusion region. Provided above the second diffusion region is a conductive member such as a capacity storage electrode, a bit line. A contact member which connects the conductive member and the second diffusion region is formed at a region where the second insulating layer is removed.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: October 17, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomofumi Shono, Akira Asai, Masanori Fukumoto
  • Patent number: 5455450
    Abstract: A bipolar lateral transistor, for example of the pnp type, is contained in a semiconductor device. The lateral transistor has a p-type emitter region and a p-type collector region laterally spaced apart by an n-type base region. This lateral transistor is formed in an n-type epitaxial layer at the surface of a p-type substrate. The transistor further has a n.sup.++ -type buried layer. The current gain in this lateral transistor is strongly increased by forming the emitter from a first partial emitter region which is weakly p-type doped and extends below an insulating layer, and a second partial emitter region which is strongly P.sup.++ -type doped and extends below the contact zone of the emitter, which is defined by an opening in the insulating layer. The respective thicknesses and doping levels of the first and second emitter regions are provided such that the first region is transparent to electrons and the second region forms a screen against electrons.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: October 3, 1995
    Assignee: U.S. Philips Corporation
    Inventor: Pierre Leduc
  • Patent number: 5446316
    Abstract: A compact package and a method of hermetically packaging a high power semiconductor device includes a metal lid bonded to a ceramic base with the semiconductor device therebetween. The lid is bonded to one surface of the device, and electrical contacts on the opposing surface of the device are bonded to foils that seal openings in the base for contact pins.
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: August 29, 1995
    Assignee: Harris Corporation
    Inventors: Victor A. K. Temple, Homer H. Glascock, II
  • Patent number: 5446312
    Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.
    Type: Grant
    Filed: June 24, 1994
    Date of Patent: August 29, 1995
    Assignee: International Business Machines Corporation
    Inventors: Chang-Ming Hsieh, Louis L. G. Hsu, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr.
  • Patent number: 5440163
    Abstract: A semiconductor integrated circuit device including a CMOS inverter which can be prevented to be destroyed due to electrostatic charges. First and second contact layers are formed just above the source and drain regions of an n-channel MOS transistor, respectively, between a first interlayer insulator film having first contact holes and a second interlayer insulator film having second contact holes. The first and second contact layers are made of material higher in electric resistance than metal, for example metal silicides. The source and drain regions of the n-channel MOS transistor are respectively contacted through the first contact holes with the first and second contact layers which are respectively contacted through the second contact holes with a metal ground wiring layer and a metal output wiring layer. The first and second interlayer insulator films have third contact holes penetrating both interlayer insulator films.
    Type: Grant
    Filed: January 5, 1995
    Date of Patent: August 8, 1995
    Assignee: NEC Corporation
    Inventor: Masayuki Ohhashi
  • Patent number: 5432371
    Abstract: A monolithically integrated circuit arrangement is arranged in a disc-shaped monocrystalline semiconductor body (100) of a first conductivity type, which semiconductor body consists of silicon and has a first and second main surface. The monolithically integrated circuit arrangement contains a vertical MOSFET power transistor (T1) which consists of a plurality of partial transistors connected in parallel and surrounded by a guard ring (4) of a second conductivity type opposite that of the semiconductor body (100). Proceeding from the first main surface (13), at least one zone (7, 8) of the conductivity type of the semiconductor body (100) but of increased impurity concentration is diffused into the guard ring (4) so as to form at least one active and/or passive peripheral circuit element (T2) which has a protective and/or regulating and/or control function.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: July 11, 1995
    Assignee: Robert Bosch GmbH
    Inventors: Volkmar Denner, Wolfgang Troelenberg, Peter Brauchle, William-Neil Fox, Neil Davies