Abstract: The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.

Abstract: Methods of making high-pixel-density LED structures are described. The methods may include forming a backplane substrate and a LED substrate. The backplane substrate and the LED substrate may be bonded together, and the bonded substrates may include an array of LED pixels. Each of the LED pixels may include a group of isolated subpixels. A quantum dot layer may be formed on at least one of the isolated subpixels in each of the LED pixels. The methods may further include repairing at least one defective LED pixel by forming a replacement quantum dot layer on a quantum-dot-layer-free subpixel in the defective LED pixel. The methods may also include forming a UV barrier layer on the array of LED pixels after the repairing of the at least one defective LED pixel.

Abstract: Porous III-nitrides having controlled/tuned optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such porous III-nitrides.

Abstract: A semiconductor memory device includes a substrate including cell and peripheral regions, a cell gate electrode disposed at the cell region, a bit line structure disposed at the cell region and including a cell conductive line and a cell line capping film disposed thereon, fin-type patterns disposed at the peripheral region, a peripheral gate electrode crossing the fin-type patterns, a peripheral gate separation pattern disposed on a sidewall of the peripheral gate electrode and having an upper surface higher than an upper surface of the peripheral gate electrode, and a peripheral interlayer insulating film covering the peripheral gate electrode, the peripheral gate separation pattern and a portion of a sidewall of the peripheral gate separation pattern. An upper surface of the peripheral interlayer insulating film and an uppermost surface of the cell line capping film are positioned at the same height relative to the substrate.

Abstract: A fabricating method for a test element group is provided. The fabricating method for a test element group includes fabricating test areas generated in a scribe lane area, wherein fabricating of the test areas includes forming a plurality of fins protruding in a first direction on a substrate, covering at least some of the plurality of fins with a masking material, and performing selective epitaxial growth by injecting a gas onto the plurality of fins. The gas is not injected onto the at least some of the plurality of fins that are covered with the masking material, such that the epitaxial growth does not occur on the fins covered with the masking material.

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the device. According to the embodiments, the semiconductor device may include: an active region extending substantially in a vertical direction on a substrate; a gate stack formed around at least a portion of an outer periphery of a middle section of the active region in the vertical direction, wherein the active region comprises a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region located on two opposite sides of the channel region in the vertical direction; a first spacer located between a conductor layer of the gate stack and the first source/drain region, and a second spacer located between the conductor layer of the gate stack and the second source/drain region.

Abstract: Provided is a display substrate. The display substrate includes: a flexible substrate, including a non-stretch region and at least one stretch region, wherein each of the at least one stretch region is proximate a boundary of the flexible substrate relative to the non-stretch region, and each of the at least one stretch region includes a first region, a second region, and a third region that are sequentially arranged in a direction going distal from the non-stretch region, and at least part of the first region and at least part of the third region have a thickness smaller than that of the second region, the second region has a thickness equal to that of the non-stretch region; and a functional film layer on one side of the flexible substrate.

Abstract: A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.

Abstract: A semiconductor device includes a first semiconductor chip in which a first multilayer wiring structure including a first coil and a second coil is formed and a second semiconductor chip in which a second multilayer wiring structure including a third coil and a fourth coil is formed. The second semiconductor chip is joined to the first semiconductor chip such that the first coil (second coil) and the third coil (fourth coil) are overlapped and the second semiconductor chip does not have an offset structure with respect to the first semiconductor chip. The second semiconductor chip is joined to the first semiconductor chip such that it is not overlapped with a pad for the first semiconductor chip and a pad for the second semiconductor chip.

Abstract: A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

Abstract: A display panel has a display area including a light-transmissive area. The display panel includes a substrate, and a plurality of shielding patterns, a plurality of light-emitting layers and a plurality of cathodes that are disposed in the light-transmissive area and on the substrate. Orthogonal projections of the plurality of shielding patterns on the substrate are separated from each other. Each light-emitting layer and a respective cathode constitute a portion of a light-emitting device. The light-emitting device has an active light-emitting area. An orthogonal projection of the active light-emitting area on the substrate is located within an orthogonal projection of a cathode of the light-emitting device on the substrate. The plurality of cathode is located at a side of a respective shielding patterns away from the substrate. An orthogonal projection of the shielding pattern on the substrate covers the orthogonal projection of the cathode on the substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.

Abstract: A semiconductor device having a transistor with fin structure includes a channel layer that is disposed over a substrate and is connected to the substrate via a semiconductor layer, a source layer that is disposed on a first side surface of the channel layer over the substrate and is separated from the substrate via a first insulating layer, a drain layer that is disposed on a second side surface of the channel layer opposite to the first side surface over the substrate and is separated from the substrate via a second insulating layer, and a gate electrode including a first portion disposed over the channel layer and a second portion which is disposed between the substrate and the channel layer and whose third side surface or fourth side surface faces the semiconductor layer.

Abstract: A semiconductor device comprises a transistor. The transistor includes: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film and containing germanium at least in an upper region of the electrode; a source region formed in the semiconductor substrate; and a drain region formed in the semiconductor substrate.

Abstract: A display device including: a substrate including a display area and a non-display area adjacent to the display area; a data driver disposed in the non-display area, and configured to provide a data voltage to the display area; a first power line disposed in the non-display area, adjacent to the data driver, and configured to transfer a first power voltage to the display area; and a cover film overlapping the data driver and the first power line, wherein the cover film includes a first layer including a first shielding portion overlapping the first power line.

Abstract: A heat spreader (3) is provided on an upper surface of a cooling plate (1) with an insulating layer (2) interposed therebetween. A semiconductor chip (4) is provided on the heat spreader (3). Mold resin (10) seals the upper surface of the cooling plate (1), the heat spreader (3), and the semiconductor chip (4). The insulating layer (2) does not protrude from the heat spreader (3) to a side of the heat spreader (3). A groove (11) is provided on the upper surface of the cooling plate (1) below a peripheral portion of the heat spreader (3). The insulating layer (2) is provided to overhang the groove (11).

Abstract: The structure of a semiconductor device with source/drain contact structures and via structures and a method of fabricating the semiconductor device are disclosed. A method for fabricating a semiconductor device includes forming a source/drain (S/D) region on a substrate, forming a S/D contact structure on the S/D region, and forming a via structure on the S/D contact structure. The forming of the via structure includes forming a via opening on the S/D contact structure, forming a non-metal passivation layer on sidewalls of the via opening, and depositing a via plug within the via opening in a bottom-up deposition process.

Abstract: A process for hydrophilic bonding first and second substrates, comprising: —bringing the first and second substrates into contact to form a bonding interface between main surfaces of the first and second substrates, and—applying a heat treatment to close the bonding interface. The process further comprises, before the step of bringing into contact, depositing, on the main surface of the first and/or second substrate, a bonding layer comprising a non-metallic material that is permeable to dihydrogen and that has, at the temperature of the heat treatment, a yield strength lower than that of at least one of the materials of the first substrate and of the second substrate located at the bonding interface. The layer has a thickness between 1 and 6 nm, and the heat treatment is carried out at a temperature lower than or equal to 900° C., and preferably lower than or equal to 600° C.

Abstract: A micro light emitting device structure includes a substrate, a connecting layer, a micro light emitting device and a covering layer. The connecting layer is connected to the substrate. The micro light emitting device is removably connected to the connecting layer, and includes a semiconductor epitaxial structure and two electrodes. The semiconductor epitaxial structure has an outer surface. The electrodes are disposed on a first surface of the outer surface of the semiconductor epitaxial structure, or disposed on the first surface of the outer surface of the semiconductor epitaxial structure and a second surface of the semiconductor epitaxial structure away from the first surface, respectively. The covering layer is disposed on the outer surface of the semiconductor epitaxial structure.

Abstract: The present invention addresses the problem of providing novel techniques for manufacturing a SiC substrate that enables reduced material loss when a strained layer is removed. The present invention is a method for manufacturing a SiC substrate 30 which includes a strained layer thinning step S1 for thinning a strained layer 12 of a SiC substrate body 10 by moving the strained layer 12 to a surface side. Including such a strained layer thinning step S1 in which the strain layer is moved to (concentrated toward) the surface side makes it possible to reduce material loss L when removing the strained layer 12.