Abstract: A memory device includes an alternating stack including insulating layers and electrically conductive layers and a tapered sidewall that laterally extends along a first horizontal direction and an inclined along a second horizontal direction, memory opening fill structures extending through each layer within the alternating stack and including memory elements and a vertical semiconductor channel, a cavity in the alternating stack bounded laterally by the tapered sidewall, and having a bottom surface including stepped surfaces of at least some of the electrically conductive layers, an insulating liner located over the tapered sidewall in the cavity, and electrically conductive strips which are adjoined to a respective one of the stepped surfaces at the bottom surface of the cavity, which extend over the insulating liner and the tapered sidewall in the cavity, and which include a respective topmost portion that is located above the topmost surface of the alternating stack.

Abstract: According to one or more embodiments, a semiconductor package includes: a first semiconductor chip including an upper surface, a lower surface, and a side surface and including a chip pad provided on the upper surface; a first cover insulating layer covering the upper surface and the side surface of the first semiconductor chip; a first upper conductive layer extending along an upper surface of the first cover insulating layer and connected to the chip pad of the first semiconductor chip; a first side conductive layer extending along a side surface of the first cover insulating layer and connected to the first upper conductive layer; a second cover insulating layer covering the first upper conductive layer, the first side conductive layer, and the first cover insulating layer; and a first lower conductive layer extending along the lower surface of the first semiconductor chip and connected to the first side conductive layer.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a first source/drain feature, a second source/drain feature and an interlayer dielectric (ILD) layer over the first and second source/drain features. The method also includes removing a portion of the ILD layer to form a cut feature opening and forming a hybrid cut feature therein to divide a to-be-formed metal layer into multiple pieces as source/drain contacts. The hybrid cut feature includes a conformal dielectric liner over the cut feature opening and a dielectric filler over the dielectric liner. During the formation of a source/drain contact opening, at least a portion of the dielectric liner extending along a sidewall of the dielectric filler is partially and selectively removed, leading to a dimension-reduced hybrid cut feature and thus a reduced spacing between two adjacent source/drain contacts.

Abstract: A semiconductor device is disclosed, comprising a first semiconductor die comprising a plurality of transistors; a second semiconductor die comprising power supply circuitry configured to generate a supply voltage for the plurality of transistors of the first semiconductor die; and a heat spreader structure. A power supply routing for a reference voltage or a power supply voltage which extends from the heat spreader structure through the second semiconductor die to the first semiconductor die.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate; a first semiconductor region and a second semiconductor region provided in the semiconductor substrate; a plurality of third semiconductor regions selectively provided in the semiconductor substrate, a plurality of first and second trenches penetrating through the second and third semiconductor regions and reaching the first semiconductor region; a plurality of gate electrodes respectively provided in the first trenches; a plurality of conductive films respectively embedded in the second trenches, junction interfaces between the first semiconductor region and the conductive films forming a plurality of Schottky barriers; a first electrode and a second electrode; and a plurality of Schottky barrier diodes that respectively include the plurality of Schottky barriers.

Abstract: An embodiment includes a device including a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first carbon-containing buffer layer on the first fin. The device also includes and a first epitaxial structure on the first carbon-containing buffer layer.

Abstract: A decoupling integrated circuit including a substrate including first and second active regions extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a first power rail configured to receive a first power supply and including a first horizontal extension being apart from the first active region in the second direction and extending in the first direction and a first-1 protrusion protruding from the first horizontal extension in a third direction opposite to the second direction, a second power rail configured to receive a second power supply and including a second horizontal extension being apart from the second active region in the second direction and extending in the first direction and a second-1 protrusion protruding from the second horizontal extension in the second direction, the first-1 protrusion and the second-1 protrusion constituting a decoupling capacitor may be provided.

Abstract: The present disclosure is related to an organic light-emitting diode apparatus. The organic light-emitting diode apparatus may include a substrate and a plurality of pixels on a first side of the substrate. Each of the plurality of pixels may include a display region and a non-display region. The non-display region may be provided with a control circuit and a first color film, and the first color film may be between the control circuit and the substrate.

Abstract: A method is provided for bonding microelectromechanical components with at least two different pressure element cavities. The method includes forming on the cap wafer or/and on the structure wafer a metal layer that allows the hermetically sealing of one cavity at a first pressure, then hermetically scaling the other cavity at a second pressure.

Abstract: A semiconductor device is provided and includes a miscut substrate, intermediate layers epitaxially grown on the miscut substrate such that an uppermost surface of the intermediate layers includes surface steps, segmented active regions including nanowire channels, each of which is epitaxially grown on a corresponding one of the surface steps and a cap layer epitaxially grown on the nanowire channels and exposed portions of the uppermost surface.

Abstract: A method for manufacturing a ball grid array (BGA) assembly is disclosed. An example method may include coating at least a portion of each solder ball of a BGA in a solder paste mix. The method may further include mounting the BGA onto a secondary board to form the BGA assembly, wherein mounting the BGA on the secondary board comprises mounting each solder ball coated with the solder paste mix to the secondary board.

Abstract: A semiconductor device includes a lower pattern extending in a first direction, and protruding from a substrate in a second direction, a lower insulating pattern on the lower pattern, and in contact with an upper surface of the lower pattern, a channel pattern on the lower insulating pattern, a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, and a source/drain pattern disposed on the lower pattern, and connected to the channel pattern. A vertical level of a lowermost portion of the source/drain pattern is lower than a vertical level of a bottom surface of the lower insulating pattern. The gate electrode overlaps the lower insulating pattern in the second direction.

Abstract: A semiconductor device includes an insulation layer, wires, a semiconductor element, and an encapsulation resin. The insulation layer includes a main surface and a back surface facing opposite in a thickness-wise direction and a side surface formed between the main surface and the back surface in the thickness-wise direction. The wires include an embedded portion embedded in the insulation layer and a redistribution portion formed of a metal film joined to the embedded portion and formed from the back surface to the side surface. The semiconductor element is mounted on the main surface and includes electrodes joined to at least part of the embedded portion of the wires. The encapsulation resin contacts the main surface and covers the semiconductor element.

Abstract: A method of forming a semiconductor device includes forming a first layer over a semiconductor fin and forming a second layer over the first layer. The first layer is a first material and the second layer is a second material different from the first layer. The second layer is thicker on a top of the semiconductor fin than along a sidewall of the semiconductor fin. The method further includes performing an oxidation process, the oxidation process oxidizing at least a portion of the second layer, and patterning the second layer and the first layer.

Abstract: A unit pixel and a displaying apparatus including the unit pixel are provided. The unit pixel includes a transparent substrate, and a plurality of light emitting devices arranged on the transparent substrate. The transparent substrate includes at least one light scattering line disposed therein so as to correspond to each of the plurality of light emitting devices.

Abstract: Embodiments of the invention include a stacked device having a first epitaxial region and a second epitaxial region vertically displaced from the first epitaxial region. The first epitaxial region comprising an asymmetric profile with a horizontal protrusion.

Abstract: Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.

Abstract: The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.

Abstract: Methods of making high-pixel-density LED structures are described. The methods may include forming a backplane substrate and a LED substrate. The backplane substrate and the LED substrate may be bonded together, and the bonded substrates may include an array of LED pixels. Each of the LED pixels may include a group of isolated subpixels. A quantum dot layer may be formed on at least one of the isolated subpixels in each of the LED pixels. The methods may further include repairing at least one defective LED pixel by forming a replacement quantum dot layer on a quantum-dot-layer-free subpixel in the defective LED pixel. The methods may also include forming a UV barrier layer on the array of LED pixels after the repairing of the at least one defective LED pixel.

Abstract: Porous III-nitrides having controlled/tuned optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such porous III-nitrides.