Abstract: Methods, non-transitory machine readable media, and computing devices that manage storage operations directed to dual-port solid state disks (SSDs) coupled to multiple hosts are disclosed. With this technology, context metadata comprising a checksum is retrieved based on a first physical address mapped, in a cached zoned namespace (ZNS) mapping table, to a logical address. The logical address is extracted from a request to read a portion of a file. A determination is made when the checksum is valid based on a comparison to identification information extracted from the request and associated with the file portion. At least the first physical address is replaced in the cached ZNS mapping table with a second physical address retrieved from an on-disk ZNS mapping table, when the determination indicates the checksum is invalid. The file portion retrieved from a dual-port SSD using the second physical address is returned to service the request.

Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

Abstract: A cache coherent interconnect connected to one or more agents, using Network Interface Units (NIUs), and also having one or more internal modules, such as a directory, is provided with one or more message builders and message receivers. These message builders and message receivers are provided as additional hardware IP blocks incorporated into the various NIUs and modules. When an agent signals an intention to enter/exit the cache coherent interconnect, a message communicating this information is generated using message builders, and transmitted using the interconnect wiring as a “virtual wire” to one or more message receivers associated with directories that need to be aware of the entry/exit transition of the agent. The directories are provided with tracking engines to manage the entry/exit information and status of the agent. Interconnects may include a broadcast engine to provide distribution to, and aggregate acknowledgements from, a single source to multiple destinations.

Abstract: The present disclosure provides a method for storing an L2P table, including the following steps: detecting the L2P table, in response to detecting update of the L2P table, acquiring a logical block address (LBA) for which a mapping relation is updated in the L2P table; sending the LBA to a journal manager; reading a corresponding physical block address (PBA) in the L2P table according to the received LBA and assembling the LBA and the corresponding PBA into delta data in response to the journal manager receiving the LBA; and saving the delta data and several basic data currently to be saved in the L2P table as a snapshot in a non-volatile memory. The present disclosure further provides a system, a computer device, and a readable storage medium.

Abstract: An integrated circuit may include orthogonal multi-phase scheduling circuitry. The scheduling circuitry may include a number of orthogonal scheduling circuits each of which is configured to receive different command types and to output a single winning command. The scheduling circuitry may further include a phase assignment circuit for receiving the winning commands from the orthogonal scheduling circuits and for assigning the received winning commands to different corresponding phase groups. Each orthogonal scheduling circuit may include command buffers, command arbiters, a global arbiter, and associated safe checking circuits.

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

Abstract: A storage device may include: a nonvolatile memory device including a plurality of memory blocks; and a memory controller for providing an external device with block count information including bitmap information representing whether an erase number of each of the plurality of memory blocks is equal to or greater than a reference value, performing an erase operation on a memory block in which data corresponding to a write command received from the external device is to be stored before the write command is executed, storing the data in the nonvolatile memory device, updating the block count information, and providing the updated block count information to the external device.

Abstract: A volume to be accessed by a host is provided. A reliability policy related to data reliability and a performance policy related to response performance to an access to the volume are set in the volume. A node that processes redundant data of data for a node that processes the data related to the volume is determined based on the reliability policy. The determined node returns a result of an access to the volume from the host according to the performance policy.

Abstract: A hardware revocation engine for invalidating a pointer, that refers to a deallocated object, from memory in a memory constrained system. The hardware revocation engine has a revocation pipeline coupled to a pipeline of a main processor of the memory constrained system. The revocation pipeline shares access to memory with the main pipeline, the revocation pipeline comprising at least a first stage and a subsequent second stage. In a first cycle of the revocation pipeline, the first stage of the revocation pipeline loads a first pointer-sized value from the memory. In a second cycle: the second stage checks whether the first loaded pointer-sized value is a pointer referring to deallocated memory. In a third cycle: in response to the outcome of the check indicating that the first loaded pointer-sized value is a pointer referring to deallocated memory, the first stage invalidates the first pointer-sized value.

Abstract: An information handling system may include a persistent memory module and a basic input/output system (BIOS). The information handling system may be configured to: prior to initialization of an operating system, receive, at a configuration application of the BIOS, configuration information regarding the persistent memory module; in response to the configuration information, allocate a first portion of the persistent memory module to volatile system memory of the information handling system, a second portion of the persistent memory module to non-volatile storage of the information handling system, and a third portion of the persistent memory module to a dynamic memory area; and after initialization of the operating system, execute a memory manager configured to alter sizes of the first portion, the second portion, and the third portion, wherein the altering is carried out without performing a reboot of the information handling system.

Abstract: Techniques are provided for microservice configuration information retrieval and storage using a generation-based cache. One method comprises obtaining, by a first microservice, a data item from a second microservice with a corresponding generation counter; maintaining, by the first microservice, the data item in a cache with the corresponding generation counter; invalidating, by the first microservice, one or more entries in the cache having a lower generation counter value than a current generation counter; and in response to a request for the data item, performing, by the first microservice: processing the requested data item, if the requested data item is in the cache after the invalidation; and if the requested data item is not in the cache after the invalidation: (i) retrieving the requested data item from the second microservice, (ii) processing the retrieved data item and (iii) placing the retrieved requested data item in the cache with a corresponding generation counter value.

Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.

Abstract: In some implementations, a memory device may resolve a set of latches of a NAND page buffer to a set of initialized values. The memory device may obtain a NAND page buffer initialized data set from the set of initialized values of the set of latches. The memory device may generate a security key using the NAND page buffer initialized data set.

Abstract: Memory with efficient storage of event log data is disclosed herein. In one embodiment, a memory device includes a non-volatile memory subsystem storing a persistent event log file, and a volatile memory subsystem including a working buffer. The memory device is configured to write newly generated event log data of the memory device to the working buffer. The memory device is further configured to write the newly generated first event log data to a first subregion of the persistent event log file. The first subregion can be one of a plurality of subregions of the persistent event log file, and can correspond to an end of event log data stored to the persistent event log file. The volatile memory subsystem can be positioned inside or outside a controller operably connected to the non-volatile memory subsystem.

Abstract: In some examples, a system computes a measure of data overwrites to a data segment stored in a storage structure, where the measure of data overwrites indicates a quantity of overwrites of data in the data segment. The system compares the measure of data overwrites to a criterion. In response to determining that the measure of data overwrites has a first relationship with respect to the criterion, the system disables data reduction for the data segment.

Abstract: A data storage device and method for multi-level conditional prediction of future random read commands are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a random read command from a host, wherein the received random read command is associated with a stream; predict a next stream to be received from the host; and predict a next random read command to be received from the host based on the received random read command and the predicted next stream. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: An approach for deleting a file from a primary file system. The approach deletes a directory entry, associated with a file, from an in-memory index associated with a secondary file system. The approach updates an index cache associated with a secondary file system, based on the in-memory index. The approach updates a dirty flag, associated with the secondary file system, to a value of TRUE.

Abstract: Configurable variable-length shift register circuits include a group of flip-flops connected in a serial configuration. The plurality of flip-flops is connected to a serial data-in line and a clock line. Each flip-flop can include a data input, a clock input configured to receive a clock signal from the clock line, and a data output. The plurality of flip-flops can include a serial data-out line. The circuit includes a plurality of multiplexers connected to the plurality of flip-flops to enable a desired number of flip-flops for an application. A nonvolatile memory can be connected to the plurality of multiplexers and configured to receive a register-length indication, where the register-length indication corresponds to a selected number of flip-flops selected for enablement for a given application.

Abstract: Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.