Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

Abstract: An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.

Abstract: Devices and techniques are disclosed wherein an end user can remotely trigger direct data management activities of a data storage device (DSD), such as creating a data snapshot, resetting a snapshot, and setting permissions at the DSD via a remote mobile device app interface.

Abstract: Methods, systems, and devices for command scheduling for a memory system are described. A memory system may be configured to analyze a received command during an initialization procedure for one or more components. In some examples, the memory system may initialize an interface and one or more processing elements as part of an initialization procedure upon transitioning from a first power mode to a second power mode. Accordingly, the command may be analyzed while the processing elements are being initialized such that, upon the processing elements being fully initialized, the command may be processed (e.g., executed).

Abstract: A data storage device and method for dynamic controller memory buffer allocation are disclosed. In one embodiment, a data storage device is provided comprising a memory and a controller with a controller memory buffer. The controller is configured to communicate with the non-volatile memory and is further configured to configure a size of the controller memory buffer; receive a request from the host to modify the size of the controller memory buffer during operation of the data storage device; and determine whether to grant the request to modify the size of the controller memory buffer. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: When a program operation to a second memory of user data in a first memory is to be performed and the size of user data is smaller than a unit program size of the second memory, final data having a size equal to the unit program size may be produced by concatenating the user data and meta data, and the final data may then programmed into the second memory. The second memory may be non-volatile memory, and the meta data may be meta data for the second memory. In some cases, dummy data may also be concatenated with the user data and meta data to produce the final data. Accordingly, it is possible to perform the program operation according to the unit program size and improve the program operation efficiency by reducing the number of program operations performed to store meta data.

Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.

Abstract: A method, computer program product, and computing system for processing a plurality of input/output (IO) requests for a storage object of a storage system. A sampling interval may be determined for the plurality of IO requests for the storage object based upon, at least in part, a machine learning model processing the plurality of IO requests. The plurality of IO requests may be sampled using the determined sampling interval. The plurality of sampled IO requests may be processed using the machine learning model.

Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.

Abstract: The present disclosure describes techniques for offloading data processing and knowledge synthesis. A set of flags may indicate information about the memory pages in a first memory and may be manageable by at least one central processing unit (CPU). A memory page may be flushed to a second memory if the memory page is associated with a first flag. The first flag may indicate that the memory page is ready to be flushed to the second memory. The second memory may be configured to store a sequence of states of each of the memory pages. Data patterns and relations among the data patterns may be determined by data processing units (DPUs) based on the sequence of states of each of the memory pages. A knowledge base may be built in a third memory based on the data patterns and the relations among the data patterns.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command; responsive to detecting that the memory access command satisfies a trigger condition, recording, in a set of registers, data associated with a plurality of events performed by processing the memory access command; and responsive to detecting that the set of registers comprises the data, disabling write operations on the set of registers.

Abstract: Methods, systems, and devices for initializing memory systems are described. A memory system may transmit, to a host system over a first channel, signaling indicative of a first set of values for a set of parameters associated with communicating information over a second channel between a storage device of the memory system and a memory device of the memory system. The host system may transmit, to the memory system, additional signaling associated with the first set of values for the set of parameters. For instance, the host system may transmit a second set of values for the set of parameters, an acknowledgement to use the first set of values, or a command to perform a training operation on the second channel to identify a second set of values for the set of parameters. The memory system may communicate the information over the second channel based on the additional signaling.

Abstract: This application describes systems and methods for facilitating memory access in flash drives. An example method performed by a memory controller may include receiving, from a host, a write command comprising data to be written into a flash memory; splitting the data into a first portion and a second portion; storing the first portion into a static random-access memory (SRAM) in the memory controller; storing the second portion into a dynamic random-access memory (DRAM) communicatively coupled with the memory controller; initiating a configuration operation corresponding to the write command; fetching the first portion from the SRAM and the second portion from the DRAM in response to the flash translation layer indicating a ready status to store the data into the flash memory; combining the fetched first portion and the fetched second portion; and storing the combined first portion and the second portion into the flash memory.

Abstract: Systems, methods, and computer readable media for preventing data loss at ephemeral and/or volatile storage of a local storage system are provided. These techniques may include synchronizing that state of the ephemeral storage system to a cloud-based storage system and capturing a cloud snapshot of the cloud-based storage system. In the event of a failure at the volatile storage, the cloud-based snapshot can be used as a restore point for the cloud-based storage system, the state of which can then be synchronized back to the volatile storage. Additionally, the local storage system includes durable storage for storing transaction logs. After synchronizing the state of the cloud-based storage system to the volatile storage, the local storage system can playback transactions in the transaction log to restore the volatile segment to the state at the time of the failure.

Abstract: A storage device includes a memory module including a memory device, a module board including a memory controller configured to control the memory device, and a memory connector disposed on one side of the module board. The storage device also includes a first enclosure disposed on a first surface of the memory module, a second enclosure disposed on a second surface opposite to the first surface of the memory module, and a first sensor disposed on the first enclosure and configured to detect a state and provide a signal for the state to the memory controller. The first enclosure includes a first long side extending in a first direction and a first short side extending in a second direction perpendicular to the first direction. A ratio of the first long side to the first short side ranges from 1.2 to 3.5.

Abstract: A method for creating a Full Data Set Directory (FDSD) entry, in accordance with one embodiment, includes acquiring a record count and file mark count of a data set written to and/or to be written to a magnetic recording tape. A writing position on the tape where the data set will be written is determined. The data set is written on the tape. An FDSD entry is generated for the data set. The FDSD entry includes information about each of the following: a tape write pass in which the data set is written, a position of the data set on the tape, the record count, and the file mark count.

Abstract: A method and a memory device are provided. A controller of the memory device retrieves a first command from a host memory. The controller stores a first identifier of the first command in a set-aside buffer of the memory device. The controller retrieves a second command from the host memory. The controller initiates processing of the first command and the second command based on a second identifier of the second command corresponding to the first identifier.

Abstract: Methods and systems for managing systems based on power consumption are disclosed. To operate data processing systems, power may be supplied to the systems. Power supply capacity may be provisioned based on the estimated power consumption for the systems. To estimate the power consumption of the systems, limits on the operation of components of the systems may be taken into account. These limits may reduce the power consumption by the components from nominal power consumption ascribed by a manufacturer. The limits may be caused by the communication architecture or other features of the systems.

Abstract: A data storage system can include a deduplicated data cache used to store unique deduplicated data portions. Data portions can be promoted to the deduplicated data cache in connection with servicing I/O operations. Servicing the I/O operation that reads data from, or writes data to, a logical address can include determining whether a data portion stored at the logical address meets criteria for promoting the data portion to a deduplicated data cache. The criteria can include a condition that the data portion is a duplicate of content stored at multiple logical addresses, and can include a condition that the data portion has a reference count that is at least a minimum threshold where the reference count denotes a number of logical addresses at which the data portion is stored. Responsive to determining the data portion meets the criteria, the data portion can be stored in the deduplicated data cache.

Abstract: A storage device, including at least one nonvolatile memory device configured to store data; and a storage controller configured to: generate a virtual table including a plurality of random values, wherein each random value of the plurality of random values designates an index from among a plurality of indexes corresponding to a plurality of main functions; transmit the virtual table to a host; receive from the host a vendor unique command (VUC) generated by the host based on the virtual table; parse the VUC based on the virtual table, perform an operation corresponding to the at least one nonvolatile memory device based on the parsed VUC; and transmit a result of the operation to the host.