Patents Examined by Nathan W. Ha
  • Patent number: 10967400
    Abstract: An ultrasonic transducer includes a membrane, a bottom electrode, and a plurality of cavities disposed between the membrane and the bottom electrode, each of the plurality of cavities corresponding to an individual transducer cell. Portions of the bottom electrode corresponding to each individual transducer cell are electrically isolated from one another. Each portion of the bottom electrode corresponds to each individual transducer that cell further includes a first bottom electrode portion and a second bottom electrode portion, the first and second bottom electrode portions electrically isolated from one another.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: April 6, 2021
    Assignee: Butterfly Network, Inc.
    Inventors: Susan A. Alie, Keith G. Fife, Joseph Lutsky, David Grosjean
  • Patent number: 10971405
    Abstract: A method for fabricating a semiconductor device includes providing a base substrate, including a first region and a second region. The first region is located on each side of the second region, and a plurality of fin structures is formed in the first region and the second region. The method includes forming a first doped region and a second doped region in the first region and the second region, respectively in the plurality of fin structures. The concentration of doping ions in the first doped region is lower than that in the second doped region, and the doping ions in the first doped region and the second doped region are the same doping type. After forming the first doped region and the second doped region, the method includes forming a plurality of gate structures on the first doped region and the second doped region across the plurality of fin structures.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 10957683
    Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seong Lee, Ah-Reum Kim, Min-Su Kim, Jong-Kyu Ryu
  • Patent number: 10950624
    Abstract: A vertical memory device includes gate electrodes on a substrate and a channel. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes, and includes a first portion, a second portion and a third portion. The second portion is formed on and connected to the first portion, and has a sidewall slanted with respect to the upper surface of the substrate so as to have a width gradually decreasing from a bottom toward a top thereof. The third portion is formed on and connected to the second portion.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Cheon Baek, Ji-Ye Noh, Yoon-Hwan Son, Ji-Sung Cheon
  • Patent number: 10950644
    Abstract: An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Sony Corporation
    Inventors: Shuji Manda, Susumu Hiyama, Yasuyuki Shiga
  • Patent number: 10943949
    Abstract: A semiconductor storage device includes a plurality of memory cells and a first circuit. The first circuit is configured to read data from a subset of the memory cells, such as a page unit or the like, then determine whether the data as read from the subset contains an error. The first circuit calculates a bit error rate for the subset if the subset contains an error and performs a recovery processing on the subset if the calculated bit error rate is less than a first threshold value but greater than a second threshold value.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yosuke Kobayashi
  • Patent number: 10943899
    Abstract: A semiconductor device includes a guard active area formed in a substrate, a plurality of transistors disposed in an element area adjacent to the guard active area, each of the transistors including an active area and a gate structure crossing the active area, and a diode transistor disposed between a first transistor and a second transistor among the transistors, and having a diode gate structure connected to the guard active area, a first active area connected to a gate structure of the first transistor, and a second active area connected to a gate structure of the second transistor.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Jeong Kim, In Mo Kim
  • Patent number: 10930612
    Abstract: A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 ?m and less than or equal to 0.8 ?m, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 ?m and less than or equal to 50 ?m, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300° C., and a content of the solvent having a boiling point of higher than or equal to 300° C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 23, 2021
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Hideo Nakako, Kazuhiko Kurafuchi, Yoshinori Ejiri, Dai Ishikawa, Chie Sugama, Yuki Kawana
  • Patent number: 10930548
    Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shane J. Trapp, Timothy A. Quick, Byeung Chul Kim
  • Patent number: 10930574
    Abstract: A semiconductor device includes a semiconductor element, a first substrate, a first electrode, a second electrode and a sealing resin. The first substrate has a first front surface and a first back surface that are spaced apart from each other in a thickness direction. The semiconductor element is mounted on the first main surface. The first electrode includes a first conductive portion and a second conductive portion. The first conductive portion is formed on a portion of the first front surface. The second conductive portion is connected to the first conductive portion and overlaps with the first substrate as viewed in a first direction perpendicular to the thickness direction. The sealing resin covers the semiconductor element. The second electrode is exposed from the sealing resin and electrically connected to the first electrode. The second electrode is in contact with the second conductive portion.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 23, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Isamu Nishimura
  • Patent number: 10930649
    Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
  • Patent number: 10923576
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Cheng-Yen Tsai, Da-Yuan Lee
  • Patent number: 10923472
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fins comprising a first fin, a second fin, a third fin, a fourth fin and a fifth fin, each of the plurality of protruding from the substrate in a first direction, and spaced apart from one another in a second direction that intersects the first direction and a plurality of trenches comprising a first trench, a second trench, a third trench and a fourth trench, each of the plurality of trenches being formed between adjacent fins of the plurality of fins, wherein variation of a first width of the first trench and a third width of the third trench is smaller than a first variation, wherein variation of a second width of the second trench and a fourth width of the fourth trench is smaller than a second variation, and wherein the second variation is greater than the first variation.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Min Kim, Dong Won Kim, Geum Jong Bae
  • Patent number: 10903217
    Abstract: An anti-fuse memory cell may include a substrate including first and second conductivity regions and an isolation region at least partially within the substrate, a program gate over the substrate, a program gate oxide layer over the isolation region and between the program gate and the substrate, a first channel region arranged laterally between the first conductivity region and the isolation region, a second channel region arranged laterally between the second conductivity region and the isolation region, a first select gate arranged over the substrate and over the first channel region and a second select gate arranged over the substrate and over the second channel region. The program gate oxide layer may be configured to break down to allow conduction between the program gate and at least one of the channel regions upon providing a program voltage difference between the program gate and at least one of the channel regions.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: January 26, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10903364
    Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Sanaz K. Gardner, Chandra S. Mohapatra, Matthew V. Metz, Gilbert Dewey, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10896873
    Abstract: A processor assembly and a system including a processor assembly are disclosed. The processor assembly includes an interposer disposed on a substrate, an integrated circuit disposed on the interposer, a memory circuit disposed on the interposer and coupled to the integrated circuit, and a capacitor embedded in the interposer. The capacitor includes at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure. The capacitor includes a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit. The capacitor includes a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit. The capacitor includes an oxide layer electrically isolating the capacitor from the interposer.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: January 19, 2021
    Assignee: Google LLC
    Inventors: Woon Seong Kwon, Nam Hoon Kim, Teckgyu Kang
  • Patent number: 10886160
    Abstract: An electronic device, e.g. an integrated circuit, includes a semiconductor substrate having a top surface and an area of the semiconductor substrate surrounded by inner and outer trench rings. The inner trench ring includes a first dielectric liner that extends from the substrate surface to a bottom of the inner trench ring, the first dielectric liner electrically isolating an interior region of the inner trench ring from the semiconductor substrate. The outer trench ring surrounds the inner trench ring and includes a second dielectric liner that extends from the substrate surface to a bottom of the outer trench ring. The second dielectric liner includes an opening at a bottom of the outer trench ring, the opening providing a path between an interior region of the outer trench ring and the semiconductor substrate.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Alexei Sadovnikov, Scott Kelly Montgomery
  • Patent number: 10886367
    Abstract: A semiconductor structure is provided that includes active semiconductor fins that have a uniform fin channel height. The uniform fin channel height is achieved by forming semiconductor fins (active and sacrificial) on an entirety of semiconductor substrate thus there is no loading effect during a subsequently performed dielectric etch step which can lead to fin channel height variation and ultimately variation in device characteristics. A trench isolation structure is located adjacent to the active semiconductor fins. The trench isolation structure includes at least one dielectric plug having a second width and a dielectric pillar having a first width located on each side of the at least one dielectric plug. The second width of the at least one dielectric plug is less than the first width of each dielectric pillar, yet equal to a width of each semiconductor fin.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Zhenxing Bi, Dexin Kong
  • Patent number: 10879073
    Abstract: One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Patent number: 10879346
    Abstract: Techniques are disclosed for forming an integrated circuit including a capacitor having a multilayer dielectric stack. For example, the capacitor may be a metal-insulator-metal capacitor (MIMcap), where the stack of dielectric layers is used for the insulator or ‘I’ portion of the MIM structure. In some cases, the composite or multilayer stack for the insulator portion of the MIM structure may include a first oxide layer, a dielectric layer, a second oxide layer, and a high-k dielectric layer, as will be apparent in light of this disclosure. Further, the multilayer dielectric stack may include an additional high-k dielectric layer, for example. Use of such multilayer dielectric stacks can enable increases in capacitance density and/or breakdown voltage for a MIMcap device. Further, use of a multilayer dielectric stack can enable tuning of the breakdown and capacitance characteristics as desired. Other embodiments may be described and/or disclosed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic