Abstract: A manufacturing method of a semiconductor device includes: a first step of, after joining a wire to an electrode using a capillary, forming a wire part by moving the capillary to a third target point while feeding out the wire; a second step of forming a bent part by moving the capillary to a fourth target point while feeding out the wire; a third step of processing the bent part into a planned cut part by repeating lowering and raising of the capillary for multiple times; and a fourth step of cutting the wire at the planned cut part by raising the capillary with a wire clamper closed to form a pin wire.

Abstract: A micromechanical component for a sensor or microphone device, including a substrate, a frame structure, which is situated on the substrate surface and/or at least one intermediate layer, and a diaphragm, which spans an inner volume, which is at least partially framed by the frame structure. The micromechanical component includes a bending beam structure, which is situated in the inner volume and includes at least one anchoring area, which is attached to the frame structure, to the substrate surface and/or to the at least one intermediate layer, and at least one self-supporting area, which is connected via at least one coupling structure to the diaphragm inner side of the diaphragm in such a way that the at least one self-supporting area is bendable by way of a warping of the diaphragm.

Abstract: In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line, a second data line, a conductive line, and a memory cell coupled to the first and second data lines. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the first and second data lines, and charge storage structure electrically separated from the first region. The second transistor includes a second region electrically separated from the first region, the second region electrically coupled to the charge storage structure and the second data line. The conductive line is electrically separated from the first and second channel regions. Part of the conductive line is spanning across part of the first region of the first transistor and part of the second region of the second transistor.

Abstract: A purpose of the present invention is to countermeasure a connection failure of an electrode in an optical sensor using PIN type photo conductive film. A structure of the present invention is as follows. A semiconductor device including an optical sensor, the optical sensor including: a thin film transistor formed on a substrate, and a photo diode formed above the thin film transistor, in which the photo diode includes an anode, a photo conductive film and a cathode, the cathode is constituted from a titanium film, and a first transparent conductive film is formed between the titanium film and the photo conductive film.

Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Abstract: A chip package structure includes a glass substrate, a routing layer, and a plurality of dies. A first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls. The routing layer is located in the glass substrate, and the solder joints are electrically connected to the substrate solder balls by using the routing layer. Each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls. The embodiments can improve connection reliability between the die and the glass substrate and can reduce a signal transmission loss.

Abstract: A monolithic integrated device may include a first device having a complementary metal-oxide-semiconductor (CMOS) substrate, and a second device arranged over the CMOS substrate. The second device may include a first conductive element, and a second conductive element arranged over the first conductive element. A via opening may extend through the first conductive element and the second conductive element of the second device to an interconnect of the CMOS substrate. A via contact may be arranged in the via opening to contact the first conductive element, the second conductive element, and the interconnect of the CMOS substrate. The via contact electrically connects the first conductive element and the second conductive element of the second device to the interconnect of the CMOS substrate.

Abstract: A device includes a transmission line structure including a signal line, a shielding structure conductive strips spaced apart from one and another and having lengthwise directions substantially perpendicular to a lengthwise direction of the signal line, a first transistor electrically coupled to the transmission line structure, and a second transistor electrically coupled to at least one of the conductive strips to control the at least one of the conductive strips to be electrically coupled to ground or electrically floating.

Abstract: A method of manufacturing a gallium nitride single-crystal substrate includes a step of grinding a main surface by arranging a grindstone and a gallium nitride single crystal having a semipolar plane or a nonpolar plane as the main surface to face each other and pressing the grindstone and the gallium nitride single crystal against each other while moving the grindstone and the gallium nitride single crystal relative to each other. The main surface is ground to make an angle formed by a direction in which the grindstone grinds the main surface and a direction obtained by projecting a c-axis of the gallium nitride single crystal onto the main surface within at least one range selected from (A)-45° or more and 45° or less; (B) 55° or more and 135° or less; and (C) ?135° or more and ?55° or less.

Abstract: A system of fabric-based devices designed as transistors with tri-state behavior that can measure any geometries on 2D and 3D surfaces. The devices are constructed from layers of conductive materials and flexible sheets that allow signals to selectively cross between layers. Multiple layers of conductive signals can be achieved by controlling the tension of the top and bottom thread, and interlayering conductive, semiconductive, insulating, and semi-porous materials around a sensing layer. The layers can be further modified to include folds and cuts that allow for 2D and 3D bending, stretching, twisting, and curves. Large sheets of devices can be organized into grid-like matrixes, with signal wires connected in a multiplexed fashion to minimize the amount of threads to simplify construction and device communication to a central processing unit.

Abstract: A system of fabric-based devices designed as transistors with tri-state behavior that can measure any geometries on 2D and 3D surfaces. The devices are constructed from layers of conductive materials and flexible sheets that allow signals to selectively cross between layers. Multiple layers of conductive signals can be achieved by controlling the tension of the top and bottom thread, and interlayering conductive, semiconductive, insulating, and semi-porous materials around a sensing layer. The layers can be further modified to include folds and cuts that allow for 2D and 3D bending, stretching, twisting, and curves. Large sheets of devices can be organized into grid-like matrixes, with signal wires connected in a multiplexed fashion to minimize the amount of threads to simplify construction and device communication to a central processing unit.

Abstract: In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.

Abstract: A method of manufacturing a laminate, the method including: providing a film-form firing material on a support sheet, the film-form firing material containing a sinterable metal particle and a binder component and having an identical or substantially identical shape and an identical size to a shape and size of a semiconductor chip; applying, to a substrate, the film-form firing material on the support sheet; peeling off the support sheet from the substrate and the film-form firing material; applying a back surface side of the semiconductor chip to the film-form firing material on the substrate to face each other; and sinter-bonding the semiconductor chip and the substrate by heating the film-form firing material to 200° C. or higher.

Abstract: A semiconductor package includes; a substrate including a first insulating layer and a first conductive pattern in the first insulating layer, a first semiconductor chip on the substrate, an interposer spaced apart from the first semiconductor chip in a direction perpendicular to an upper surface of the substrate and including a second insulating layer and a second conductive pattern in the second insulating layer, a first element between the first semiconductor chip and the interposer, a connection member between the substrate and the interposer, and a mold layer covering side surfaces of the first semiconductor chip and side surfaces of the first element.

Abstract: A method for producing singulated encapsulated components. The method includes the steps of application of a frame structure on a substrate surface of a substrate, wherein the frame structure surrounds components arranged on the substrate surface; bonding of a cover substrate on the frame structure; hardening of the frame structure; and singulation of the encapsulated components, wherein the frame structure is formed from an adhesive.

Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.

Abstract: Device and method for using a semiconductor component in which a dielectric layer is situated between a first electrode and a second electrode of the semiconductor component, defects of a first defect type being present in the dielectric layer. The method includes: operating the semiconductor component using a first voltage having a first polarity between the first electrode and the second electrode, determining whether or not a condition is met for switching over from operating the semiconductor component using the first voltage to operating the semiconductor component using a second voltage, which has a second polarity opposite the first polarity, continuing the operation of the semiconductor component using the first voltage if the condition is not met, and otherwise ending the operation of the semiconductor component using the first voltage, and operating the semiconductor component using the second voltage between the first electrode and the second electrode.

Abstract: The present disclosure generally relates to trench isolation structures for semiconductor devices. More particularly, the present disclosure relates to semiconductor devices having trench isolation structures with varying depths for electrically isolating integrated circuit (IC) components in the semiconductor devices. The present disclosure also relates to method of forming the trench isolation structures.

Abstract: A method of forming a package device includes providing a carrier substrate, forming a trench in a front side of the carrier substrate, and bonding a semiconductor die in the trench. The method also includes thinning a back side of the carrier substrate based on a target thickness to obtain a thinned carrier substrate. The method further includes providing a first die group and bonding the thinned carrier substrate to the first die group to form a height-adjusted first die group.