Patents Examined by Nathau W. Ha
  • Patent number: 6531738
    Abstract: In an SOI (Silicon On Insulator) semiconductor device, a first semiconductor layer overlies a semiconductor substrate so as to sandwich an insulating layer, and second and third semiconductor layers with a different conductivity type from the second semiconductor layer are formed on the surface of the first semiconductor layer. At the interface between the first semiconductor layer and the insulating layer, a fourth semiconductor layer with a different conductivity type from the first semiconductor layer is formed. The fourth semiconductor layer includes an impurity of larger than 3×1012/cm2 so as not to be completely depleted even though a reverse bias voltage is applied between the second and third semiconductor layers.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: March 11, 2003
    Assignee: Matsushita ElectricIndustrial Co., Ltd.
    Inventors: Yasuhiro Uemoto, Katsushige Yamashita, Takashi Miura