Abstract: An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

Abstract: A power-supply control device includes: a distribution adjustment unit adjusting electric energy; and a loss comparison unit comparing losses in power running and regeneration and determining, with respect to power running and regeneration, whether a loss in a current state is smaller. Further, the distribution adjustment unit adjusts the electric energy by performing the distribution in accordance with the remaining capacity ratio in the current state in a case where it is determined that the loss in power running is smaller when the current state is a power running state or in a case where it is determined that the loss in regeneration is smaller when the current state is a regeneration state.

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

Abstract: A method for designing an integrated circuit includes steps of selecting a power rail of a cell, determining that a clearance distance for an electrical connection to or around the power rail is not sufficient to fit the electrical connection, selecting a power rail portion of the power rail for modification, and modifying a shape of the power rail portion to provide a clearance distance sufficient to fit the electrical connection. As clearance distances between features in an interconnection structure of an integrated circuit become smaller, manufacturing becomes more difficult and error-prone. Increasing clearance distances improves manufacturability of an integrated circuit. Modifying the shape of an integrated circuit power rail increases clearance distance to and/or around a power rail.

Abstract: An electronic unit includes an electricity reception section that receives power transmitted using one of a magnetic field or an electric field, a secondary battery that is charged based on a received power received by the electricity reception section, and a state notification section that provides notification to outside as to a state of its own unit. A charging period during which the secondary battery is charged based on the received power and a non-charging period are set in a time-divisional manner. The state notification section notifies of the unit state based on the received power in both of the charging period and the non-charging period.

Abstract: A charging station for charging electrical vehicles and comprising battery pack(s). The battery pack(s) comprise(s) batteries coupled in series and a control unit for controlling the batteries individually. Each battery (1) comprises battery cell(s) with a battery inlet line and a battery outlet line, an electrical circuit element arranged to lead from the battery inlet line to the battery outlet line to form an electrical path leading around the battery cell, and one switch. The switch is arranged in the battery outlet line or the battery inlet line and is switchable between first and second positions. The control unit is connected to the switch of each battery and is adapted for controlling the switch to switch between the first position, in which an electrical power is lead through the battery cell, and the second position, in which the electrical power is lead through the electrical circuit element.

Abstract: A hybrid electronic system including an emulator side including a processor and a first clock, a simulated side including one or more models to simulate one or more prototypes and a second clock, a first interface to the emulator side, and a second interface to the simulated side is disclosed. The processor is configured to determine using the first interface a first amount of time corresponding to an amount of time advanced on the emulator side by the first clock. The processor is configured to determine using the second interface a second amount of time corresponding to an amount of time advanced on the simulated side by the second clock, and set a value of a clock frequency of the second clock based on an initial value of the clock frequency of the second clock and a ratio of the first amount of time to the second amount of time.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.

Abstract: A method of charging a secondary battery, including first, second and third charging sections in which a CC-charging performed as first, second, and third Crate (C1, C2, C3), respectively, is supplied until the voltage of the secondary battery reaches a respective first, second and third charging cutoff voltage (V1), (V2), (V3) and a CV-charging is performed as the respective charging C-rate gradually decreases in response to reaching the respective charging cutoff voltage (V1), (V2), (V3), wherein the charging cutoff voltage satisfies the V1=n?(0.25˜0.15), V2 n?(0.2˜0.1), and V3=n (here, ‘n’ is an electric potential at the full charge of the secondary battery), and V1<V2<V3.

Abstract: Verification for a design can include, for a covergroup corresponding to a variable of the design, generating a state coverage data structure specifying a plurality of transition bins. Each transition bin can include a sequence. Each sequence can specify states of the variable to be traversed in order during simulation of the design. Verification can include generating a state sequence table configured to use state values as keys and one or more of the sequences as data for the respective keys, and during simulation of the design, maintaining a sequence list specifying each sequence that is running based on sample values of the variable. Hit counts for the transition bins can be updated during the simulation.

Abstract: An electrochemical cell management system comprising an electrochemical cell and at least one controller configured to control the cell such that, for at least a portion of a charge cycle, the cell is charged at a charging rate or current that is lower than a discharging rate or current of at least a portion of a previous discharge cycle. An electrochemical cell management method. An electrochemical cell management system comprising an electrochemical cell and at least one controller configured to induce a discharge of the cell before and/or after a charging step of the cell. An electrochemical cell management method. A electrochemical cell management system comprising an electrochemical cell and at least one controller configured to: monitor at least one characteristic of the cell and, based on the at least one characteristic of the cell, induce a discharge and/or control a charging rate or current of the cell.

Abstract: A recharging method and assembly to charge an electric vehicle comprising a battery pack including a plurality of storage batteries having a same nominal charge voltage, the battery pack being connectable to a recharging station adapted to provide a recharging voltage, which is greater than said nominal charge voltage. In a recharging mode, in which the recharging voltage deliverable by the recharging station is equal to or greater than the sum of the nominal charge voltages of the plurality of storage batteries, the storage batteries are connected in series to one another, so as to recharge the series of batteries with a recharging voltage greater than the nominal charge voltage.

Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.

Abstract: A method includes specifying a target memory macro with one or more parameters, finding function-blocks in the target memory macro, and determining failure rates of the function-blocks based on an amount of transistors and area distributions in a collection of base cells. The method includes generating a failure-mode analysis for the target memory macro, from a memory compiler, based on the failure rates of the function-blocks. The method includes determining a safety level of the target memory macro, based upon the failure-mode analysis of the target memory macro.

Abstract: Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. Design management component (DMC) can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, the parameters determined based on random seed values; simulate responses of the sample timing paths; and generate vectorized data based on the simulated responses. DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. Static timing analysis (STA) component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.