Abstract: According to embodiments, a light emitting display device includes a substrate, a first anode and a second anode positioned on the substrate, a plurality of conductive layers, at least one semiconductor layer, and a plurality of insulating layers positioned between the substrate and the first anode and between the substrate and the second anode, wherein the plurality of conductive layers includes a capacitor triple layer, a first overlapping wiring, and a second overlapping wiring, the first overlapping wiring and the second overlapping wiring overlap at least partially on a plane, at least a portion of the first anode overlaps the capacitor triple layer on a plane, and a first portion of the second anode overlaps the first overlapping wiring and the second overlapping wiring.

Abstract: A semiconductor structure includes a first gate-all-around field effect transistor, which in turn includes an upper nanosheet and a first gate structure. The first gate structure is laterally confined by first gate spacers and surrounds the upper nanosheet. The first gate structure includes a first gate dielectric on the upper nanosheet and a u-shaped first high-k material on a lower portion of the first gate spacers and on the first gate dielectric.

Abstract: A microelectronic device comprises a stack structure, and slot structures vertically extending through the stack structure and dividing the stack structure into block structures. Each of the slot structures individually comprises an insulative liner material vertically extending through the slot structure and contacting sidewalls of the insulative levels and the conductive levels defining the slot structure, and grains of a material in contact with sidewalls of the insulative liner material. The grains of the material comprise first grains spanning an entire width between the sidewalls of the insulative liner material. Related memory devices, electronic systems, and methods are also described.

Abstract: Provided as an electronic device and an electronic apparatus including the electronic device. The electronic device includes a conductive material layer, a mixed material layer covering the conductive material layer, and an electrode layer covering the mixed material layer. The mixed material layer includes an orthorhombic crystal phase and a tetragonal crystal phase mixed therein such that a ferroelectric material and an anti-ferroelectric material coexist therein.

Abstract: Embodiments of this disclosure provide a method of manufacturing a semiconductor, including the following steps. A substrate comprising an active layer on the substrate is provided, and the substrate is defined with an array area and a peripheral area surrounding the array area. A first film layer is formed on the active layer. A second film layer is formed on the first film layer. An anti-reflection tri-layer stack containing a capacitor pattern is formed on the second film layer, and the anti-reflection tri-layer stack includes a nitrogen-free anti-reflection layer. A photoresist mask is formed on the anti-reflection tri-layer stack to expose the anti-reflection tri-layer stack in the array area. A lithography process id performed on the photoresist mask and the anti-reflection tri-layer stack in the array area. Trenches are formed in the second film layer and the first film layer in the array area based on the capacitor pattern.

Abstract: A method of manufacturing an electronic device comprising the following successive steps: a) forming a structure comprising a diode stack disposed on a first substrate, and a sacrificial layer of semiconductor material interposed between the first substrate and the diode stack; b) transferring the structure to a second substrate; and c) removing the first substrate by electropolishing the sacrificial layer by applying a bias voltage to the sacrificial layer via the diode stack.

Abstract: A semiconductor device includes an integrated circuit and one or more guard rings around the integrated circuit in a top view of the semiconductor device. At least one guard ring of the one or more guard rings includes an active region in the substrate, a first plurality of elongated conductive structures extending in a first direction in the top view of the semiconductor device and arranged in a second direction in the top view of the semiconductor device, and a second plurality of elongated conductive structures extending in the second direction and arranged in the first direction. The combination of the first and second pluralities of elongated conductive structures forms a conductive grid above the active region, and provides increased coverage of the surface area of the active region relative to including only the first plurality of elongated conductive structures or only the second plurality of elongated conductive structures.

Abstract: A light emitting element includes a first semiconductor layer; an active layer; a second semiconductor layer; a first electrode; and a second electrode. The active layer includes a first surface contacting the first semiconductor layer, a second surface facing the first surface and contacting the second semiconductor layer, and a side connected to the first surface and the second surface. The first semiconductor layer includes partitioned first, second, and third areas. A side of the first area is inclined in a same direction as the side of the active layer, a side of the second area is inclined in a direction opposite to the direction in which the side of the active layer is inclined, and a side of the third area includes a straight line part parallel to the length direction of the light emitting element.

Abstract: Provided is a semiconductor device for video transmission display including a display unit including a plurality of light emitting elements constituting a plurality of unit display pixels, an image sensor unit disposed on the display unit so that the plurality of unit image sensor pixels corresponding to the same color and the plurality of unit display pixels overlap each other at least partially in a vertical direction, and a plurality of connection paths each including at least one through electrode and electrically connecting the plurality of unit image sensor pixels corresponding to the same color to the plurality of unit display pixels.

Abstract: A 3D integrated circuit structure includes a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material encapsulating the first semiconductor chip die and the plurality of core balls on the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure. A footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.

Abstract: A semiconductor device having a plurality of layers deposited on a substrate and extending in at least one lateral aspect defined by a lateral axis thereof comprises at least one low(er)-index coating disposed on a first layer surface and at least one EM radiation-modifying layer embedded within the at least one low(er)-index coating and comprising at least one particle structure comprising a deposited material. Embedding the at least one particle structure of the at least one EM radiation-modifying layer within the at least one low(er)-index coating modifies the absorption spectrum of the at least one EM radiation-modifying layer for EM radiation passing at least partially therethrough at a non-zero angle relative to the lateral aspect therein in at least a part of the EM spectrum.

Abstract: A tandem light-emitting device that can be used in a high-resolution display apparatus is provided. The light-emitting device includes a first electrode, a second electrode, and an organic compound layer. The organic compound layer is positioned between the first electrode and the second electrode; the organic compound layer includes a first light-emitting unit, a second light-emitting unit, and an intermediate layer; the intermediate layer is positioned between the first light-emitting unit and the second light-emitting unit; the first light-emitting unit is positioned between the first electrode and the intermediate layer; the first light-emitting unit includes a first light-emitting layer and a first electron-transport layer; the first electron-transport layer is in contact with the intermediate layer; the intermediate layer is configured to block holes moving from the first electrode side to the second electrode side; and the first electron-transport layer is a layer having a bipolar property.

Abstract: A manufacturing method of a heat dissipation layer is provided. A first carrier substrate and a second carrier substrate creating a first confined space therebetween are provided. A first seed layer is formed on the first carrier substrate and a second seed layer is formed on the second carrier substrate. A first heat dissipation layer is formed from the first seed layer and the second seed layer in the first confined space. The second carrier substrate is removed from the first heat dissipation layer.

Abstract: Dielectric material layers and an insulating layer may be formed over a semiconductor substrate containing a semiconductor region. A via opening may be etched through at least the insulating layer. A metal layer may be deposited and patterned to provide a heater element of a phase change memory (PCM) switch and an electrostatic discharge metal structure that fills the via opening. A phase change material layer may be deposited over the heater element and the electrostatic discharge metal structure. The phase change material layer may be patterned into a phase change material portion by performing an anisotropic etch process. An electrostatic discharge path including the electrostatic discharge metal structure and the doped semiconductor region discharges electrostatic charges that accumulate in the insulating layer into the semiconductor substrate during the anisotropic etch process.

Abstract: A display device includes: a substrate in which a main display area, a first non-display area inside the main display area, and an auxiliary display area between the main display area and the first non-display area are defined; and a display unit including an auxiliary display and a main display. The auxiliary display is disposed on the auxiliary display area and includes a plurality of first auxiliary pixels, a plurality of second auxiliary pixels, and a plurality of third auxiliary pixels. The main display is disposed on the main display area and includes a plurality of main pixels. The plurality of first auxiliary pixels is commonly driven by a first driving signal, the plurality of second auxiliary pixels is commonly driven by a second driving signal, and the plurality of third auxiliary pixels is commonly driven by a third driving signal.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device may include a substrate including first and second cell active patterns and a dummy active pattern, a cell gate dielectric layer on the first and second cell active patterns and the dummy active pattern, a first cell gate conductive layer on the cell gate dielectric layer, and a bit-line structure connected to the first cell active pattern. A distance between the second cell and dummy active patterns is less than that between the first cell and dummy active patterns. The first cell gate conductive layer may include a dummy overlap section overlapping the dummy active pattern and the second cell active pattern, and a cell overlap section overlapping the first cell active pattern. A top surface of the dummy overlap section may be at a level higher than that of a top surface of the cell overlap section.

Abstract: A method for manufacturing a semiconductor device includes: forming a channel portion which includes a semiconductor material; sequentially forming a first oxide film and a second oxide film on the channel portion, the first oxide film and the second oxide film being made of different materials, one of the first oxide film and the second oxide film including a rare-earth metal; performing a treatment such that the first oxide film and the second oxide film are formed into an interfacial layer which includes a first dielectric material and which is formed on the channel portion; forming a gate dielectric layer which includes a second dielectric material and which is formed on the interfacial layer, the second dielectric material being different from the first dielectric material; and forming a gate electrode on the gate dielectric layer.

Abstract: A semiconductor device includes a substrate having a front surface including an active region and a rear surface opposite to the front surface. An active pattern is on the active region. A gate structure extends in a second direction on the active region. Source/drain regions are disposed on the active pattern on both sides of the gate structure. A front interconnection structure is disposed on the gate structure and the source/drain regions. A rear interconnection structure is disposed on the rear surface of the substrate. A target region defined by the source/drain regions and the active pattern includes a non-oxidizing material at a first concentration. The non-oxidizing material is injected during a high-pressure heat treatment process. A rear interconnection region defined by the substrate, the rear through-structure, and the rear interconnection structure includes the non-oxidizing material at a second concentration higher than the first concentration.

Abstract: A semiconductor device includes a plurality of conductive members including a die pad, a first semiconductor element and a second semiconductor element each located on the die pad, an insulating element electrically connected to the first semiconductor element and the second semiconductor element and insulating the first semiconductor element and the second semiconductor element from each other, and an insulating substrate interposed between the die pad and the insulating element and bonded to the die pad. The insulating element is bonded to the insulating substrate.

Abstract: A display apparatus including link wirings and at least one moisture blocking layer is provided. An upper interlayer insulating layer and a device protection layer may be disposed on the link wirings between a display area and a pad area. A power voltage supply line may be disposed between the upper interlayer insulating layer and the device protection layer. An encapsulating dam and an upper planarization layer may be disposed on the device protection layer. The upper planarization layer may be disposed outside a dam area overlapping with the encapsulating dam. The at least one moisture blocking layer may include a first moisture blocking layer between the pad area and the encapsulating dam and/or a second moisture blocking layer between the encapsulating dam and the display area. The first moisture blocking layer and the second moisture blocking layer may overlap an end of the upper planarization layer.