Patents Examined by Nduka E Ojeh
  • Patent number: 12765382
    Abstract: A semiconductor device includes an integrated circuit and one or more guard rings around the integrated circuit in a top view of the semiconductor device. At least one guard ring of the one or more guard rings includes an active region in the substrate, a first plurality of elongated conductive structures extending in a first direction in the top view of the semiconductor device and arranged in a second direction in the top view of the semiconductor device, and a second plurality of elongated conductive structures extending in the second direction and arranged in the first direction. The combination of the first and second pluralities of elongated conductive structures forms a conductive grid above the active region, and provides increased coverage of the surface area of the active region relative to including only the first plurality of elongated conductive structures or only the second plurality of elongated conductive structures.
    Type: Grant
    Filed: February 15, 2024
    Date of Patent: October 13, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Yu Huang, Shih-Fan Chen, Sheng-Fu Hsu
  • Patent number: 12765163
    Abstract: A light emitting element includes a first semiconductor layer; an active layer; a second semiconductor layer; a first electrode; and a second electrode. The active layer includes a first surface contacting the first semiconductor layer, a second surface facing the first surface and contacting the second semiconductor layer, and a side connected to the first surface and the second surface. The first semiconductor layer includes partitioned first, second, and third areas. A side of the first area is inclined in a same direction as the side of the active layer, a side of the second area is inclined in a direction opposite to the direction in which the side of the active layer is inclined, and a side of the third area includes a straight line part parallel to the length direction of the light emitting element.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: October 13, 2026
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myeong Su So, Seul Ki Kim, Si Sung Kim, Chi Hun Won
  • Patent number: 12765221
    Abstract: Provided is a semiconductor device for video transmission display including a display unit including a plurality of light emitting elements constituting a plurality of unit display pixels, an image sensor unit disposed on the display unit so that the plurality of unit image sensor pixels corresponding to the same color and the plurality of unit display pixels overlap each other at least partially in a vertical direction, and a plurality of connection paths each including at least one through electrode and electrically connecting the plurality of unit image sensor pixels corresponding to the same color to the plurality of unit display pixels.
    Type: Grant
    Filed: February 15, 2024
    Date of Patent: October 13, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myeongeon Kim, Bumsuk Kim, Jungchak Ahn, Kyungho Lee
  • Patent number: 12765435
    Abstract: A 3D integrated circuit structure includes a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material encapsulating the first semiconductor chip die and the plurality of core balls on the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure. A footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: October 13, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choongbin Yim, Jongkook Kim, Chengtar Wu
  • Patent number: 12765211
    Abstract: A semiconductor device having a plurality of layers deposited on a substrate and extending in at least one lateral aspect defined by a lateral axis thereof comprises at least one low(er)-index coating disposed on a first layer surface and at least one EM radiation-modifying layer embedded within the at least one low(er)-index coating and comprising at least one particle structure comprising a deposited material. Embedding the at least one particle structure of the at least one EM radiation-modifying layer within the at least one low(er)-index coating modifies the absorption spectrum of the at least one EM radiation-modifying layer for EM radiation passing at least partially therethrough at a non-zero angle relative to the lateral aspect therein in at least a part of the EM spectrum.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: October 13, 2026
    Assignee: OTI Lumionics Inc.
    Inventors: Michael Helander, Zhibin Wang, Yi-Lu Chang, Qi Wang, Yingjie Zhang
  • Patent number: 12765165
    Abstract: A tandem light-emitting device that can be used in a high-resolution display apparatus is provided. The light-emitting device includes a first electrode, a second electrode, and an organic compound layer. The organic compound layer is positioned between the first electrode and the second electrode; the organic compound layer includes a first light-emitting unit, a second light-emitting unit, and an intermediate layer; the intermediate layer is positioned between the first light-emitting unit and the second light-emitting unit; the first light-emitting unit is positioned between the first electrode and the intermediate layer; the first light-emitting unit includes a first light-emitting layer and a first electron-transport layer; the first electron-transport layer is in contact with the intermediate layer; the intermediate layer is configured to block holes moving from the first electrode side to the second electrode side; and the first electron-transport layer is a layer having a bipolar property.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: October 13, 2026
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeyoshi Watabe, Nobuharu Ohsawa, Hiromi Seo
  • Patent number: 12765393
    Abstract: A manufacturing method of a heat dissipation layer is provided. A first carrier substrate and a second carrier substrate creating a first confined space therebetween are provided. A first seed layer is formed on the first carrier substrate and a second seed layer is formed on the second carrier substrate. A first heat dissipation layer is formed from the first seed layer and the second seed layer in the first confined space. The second carrier substrate is removed from the first heat dissipation layer.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: October 13, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Hao Jhang, Yu-Hsiang Yen, Wei-Yen Woon
  • Patent number: 12757643
    Abstract: Dielectric material layers and an insulating layer may be formed over a semiconductor substrate containing a semiconductor region. A via opening may be etched through at least the insulating layer. A metal layer may be deposited and patterned to provide a heater element of a phase change memory (PCM) switch and an electrostatic discharge metal structure that fills the via opening. A phase change material layer may be deposited over the heater element and the electrostatic discharge metal structure. The phase change material layer may be patterned into a phase change material portion by performing an anisotropic etch process. An electrostatic discharge path including the electrostatic discharge metal structure and the doped semiconductor region discharges electrostatic charges that accumulate in the insulating layer into the semiconductor substrate during the anisotropic etch process.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: October 6, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Liang Chu, Hung-Ju Li, Yi Ching Ong, Kuo-Chyuan Tzeng, Kuo-Ching Huang, Harry-Hak-Lay Chuang
  • Patent number: 12751168
    Abstract: A display device includes: a substrate in which a main display area, a first non-display area inside the main display area, and an auxiliary display area between the main display area and the first non-display area are defined; and a display unit including an auxiliary display and a main display. The auxiliary display is disposed on the auxiliary display area and includes a plurality of first auxiliary pixels, a plurality of second auxiliary pixels, and a plurality of third auxiliary pixels. The main display is disposed on the main display area and includes a plurality of main pixels. The plurality of first auxiliary pixels is commonly driven by a first driving signal, the plurality of second auxiliary pixels is commonly driven by a second driving signal, and the plurality of third auxiliary pixels is commonly driven by a third driving signal.
    Type: Grant
    Filed: April 29, 2024
    Date of Patent: September 29, 2026
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwang Sae Lee, Ki Myeong Eom
  • Patent number: 12751003
    Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device may include a substrate including first and second cell active patterns and a dummy active pattern, a cell gate dielectric layer on the first and second cell active patterns and the dummy active pattern, a first cell gate conductive layer on the cell gate dielectric layer, and a bit-line structure connected to the first cell active pattern. A distance between the second cell and dummy active patterns is less than that between the first cell and dummy active patterns. The first cell gate conductive layer may include a dummy overlap section overlapping the dummy active pattern and the second cell active pattern, and a cell overlap section overlapping the first cell active pattern. A top surface of the dummy overlap section may be at a level higher than that of a top surface of the cell overlap section.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: September 29, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eunjung Kim
  • Patent number: 12751047
    Abstract: A method for manufacturing a semiconductor device includes: forming a channel portion which includes a semiconductor material; sequentially forming a first oxide film and a second oxide film on the channel portion, the first oxide film and the second oxide film being made of different materials, one of the first oxide film and the second oxide film including a rare-earth metal; performing a treatment such that the first oxide film and the second oxide film are formed into an interfacial layer which includes a first dielectric material and which is formed on the channel portion; forming a gate dielectric layer which includes a second dielectric material and which is formed on the interfacial layer, the second dielectric material being different from the first dielectric material; and forming a gate electrode on the gate dielectric layer.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: September 29, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shen-Yang Lee, Hsiang-Pi Chang
  • Patent number: 12745618
    Abstract: A semiconductor device includes a substrate having a front surface including an active region and a rear surface opposite to the front surface. An active pattern is on the active region. A gate structure extends in a second direction on the active region. Source/drain regions are disposed on the active pattern on both sides of the gate structure. A front interconnection structure is disposed on the gate structure and the source/drain regions. A rear interconnection structure is disposed on the rear surface of the substrate. A target region defined by the source/drain regions and the active pattern includes a non-oxidizing material at a first concentration. The non-oxidizing material is injected during a high-pressure heat treatment process. A rear interconnection region defined by the substrate, the rear through-structure, and the rear interconnection structure includes the non-oxidizing material at a second concentration higher than the first concentration.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: September 22, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungmin Lim, Jinnam Kim, Jongmin Baek, Hyoseok Choi
  • Patent number: 12745655
    Abstract: A semiconductor device includes a plurality of conductive members including a die pad, a first semiconductor element and a second semiconductor element each located on the die pad, an insulating element electrically connected to the first semiconductor element and the second semiconductor element and insulating the first semiconductor element and the second semiconductor element from each other, and an insulating substrate interposed between the die pad and the insulating element and bonded to the die pad. The insulating element is bonded to the insulating substrate.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: September 22, 2026
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshizo Osumi, Hiroaki Matsubara, Tomohira Kikuchi, Taro Nishioka
  • Patent number: 12745523
    Abstract: A display apparatus including link wirings and at least one moisture blocking layer is provided. An upper interlayer insulating layer and a device protection layer may be disposed on the link wirings between a display area and a pad area. A power voltage supply line may be disposed between the upper interlayer insulating layer and the device protection layer. An encapsulating dam and an upper planarization layer may be disposed on the device protection layer. The upper planarization layer may be disposed outside a dam area overlapping with the encapsulating dam. The at least one moisture blocking layer may include a first moisture blocking layer between the pad area and the encapsulating dam and/or a second moisture blocking layer between the encapsulating dam and the display area. The first moisture blocking layer and the second moisture blocking layer may overlap an end of the upper planarization layer.
    Type: Grant
    Filed: January 12, 2024
    Date of Patent: September 22, 2026
    Assignee: LG Display Co., Ltd.
    Inventors: Ye In Hong, Jun Young Kwon
  • Patent number: 12740329
    Abstract: The invention relates to the field of superconducting integrated circuits. The invention includes an integrated circuit device comprising a substrate, a Josephson junction on the substrate, external electrodes on the substrate and spaced apart from the Josephson junction, and bridge connections connecting the Josephson junction to the external electrodes. The invention also includes a method for manufacturing such an integrated circuit device.
    Type: Grant
    Filed: September 22, 2023
    Date of Patent: September 15, 2026
    Assignee: IQM Finland Oy
    Inventors: Wei Qiu, Wei Liu, Tianyi Li
  • Patent number: 12740464
    Abstract: A laser transfer method includes transferring a pad of conductive paste from a conductive-paste layer on a first donor substrate to a receiver substrate by laser-induced forward transfer, and transferring a microelectronic device from a second donor substrate to the pad of conductive paste on the receiver substrate by laser-induced forward transfer. The two steps of laser-induced forward transfer may be performed in the same laser-based machine. The presently disclosed method is applicable to the manufacture of microLED displays. In this context, the disclosed method may yield significant cost reductions, at least by virtue of requiring fewer processing steps and tools than conventional schemes.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: September 15, 2026
    Assignee: Coherent LaserSystems GmbH & Co. KG
    Inventor: Muhammad Fatahilah
  • Patent number: 12733095
    Abstract: A substrate comprising a core layer, at least one first dielectric layer coupled to a first surface of the core layer, at least one second dielectric layer coupled to a second surface of the core layer, a plurality of interconnects located at least partially in the at least one first dielectric layer; a region comprising a plurality of block interconnects of an interconnect block; and a solder resist layer coupled to the at least one first dielectric layer.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: September 8, 2026
    Assignee: QUALCOMM INCORPORATED
    Inventors: Hong Bok We, Joan Rey Villarba Buot, Sang-Jae Lee, Zhijie Wang
  • Patent number: 12733348
    Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk in a display, a cutting structure may disrupt continuity of the OLED layers. The cutting structure may have two undercuts to disrupt continuity of at least some of the OLED layers. The cutting structure may include a conductive portion that provides a cathode voltage to a cathode layer for the OLED pixels.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: September 8, 2026
    Inventors: Siddharth Harikrishna Mohan, Gwanwoo Park, Ping Kuen Daniel Tsang, Pei Yin, Weixin Li, Li-An Liu, Alexandru Riposan, Teruo Sasagawa, Steven J Brewer, Younggu Lee, Mitsuhiro Kashiwabara, Rui Liu, Hung-Yi Tsai, Tien-Pei Chou, Yi Wen Wang, Mahendra Chhabra, Chieh Hung Yang, Bhadrinarayana Lalgudi Visweswaran, David K Schoenwald
  • Patent number: 12721142
    Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to isolated self-aligned super vias. According to one embodiment, a super via device can comprise a super via structure, a metallic line and a dielectric fill material located between the sidewalls of the super via structure and the metallic line.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: August 25, 2026
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koichi Motoyama, Ruilong Xie, Nicholas Anthony Lanzillo
  • Patent number: 12720954
    Abstract: A display device includes a plurality of pixels disposed on a substrate, in which each pixel includes a first subpixel, a second subpixel adjacent to the first subpixel, and a third subpixel adjacent to the second subpixel, the second subpixel disposed between the first subpixel and the third subpixel. A first color filter is disposed in the first subpixel, and is configured to emit light having a first color, a second color filter is disposed in the second subpixel, and is configured to emit light having a second color, and a third color filter is disposed in the third subpixel, and is configured to emit light having a third color. Further, an upper surface of the second color filter is disposed a greater distance from the substrate than an upper surface of the first color filter.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: August 25, 2026
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Ho-Jin Kim, Minki Kim