Abstract: A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.

Abstract: A display device includes a first base, a pixel electrode on the first base, a pixel defining layer having an opening that at least partially exposes the pixel electrode, a light emitting layer on the pixel electrode, an auxiliary electrode on the same layer as the pixel electrode, a partition wall on the auxiliary electrode that at least partially exposes a side surface of the auxiliary electrode, an organic layer on the partition wall, and a common electrode continuously arranged on the light emitting layer and the organic layer, wherein a side surface of the partition wall has a reverse-tapered shape, and the common electrode contacts the side surface of the auxiliary electrode.

Abstract: Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.

Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

Abstract: A display device includes a scan line extending in a first direction. A plurality of data lines cross the scan line. A driving voltage line crosses the scan line. An active pattern includes a plurality of channel regions and a plurality of conductive regions. A control line is connected to the plurality of data lines and the driving voltage line. The active pattern includes a shielding part overlapping at least one data line of the plurality of data lines. The control line includes a plurality of main line parts each extending in the first direction, and a detour part connecting two adjacent main line parts of the plurality of main line parts to each other. The detour part extends along a periphery of the active pattern and crosses the at least one data line of the plurality of data lines.

Abstract: Data rate that can be supported by a photodetector can be limited by the aperture size of the photodetector. In some embodiments, the minimum aperture diameter can be about 30 um. This limitation is due, for example, to an inability of the optics to focus the beam to a smaller spot, and the mechanical tolerances of the assembly process. The techniques described in the present disclosure can reduce the optical spot size and improve on the mechanical tolerances that are achievable, thereby improving the photodetector and VCSEL manufacturing processes and systems. A photodetector or VCSEL system design with higher data rate and lower production cost can be achieved using the techniques described herein.

Abstract: A method includes disposing a layer stack on a substrate, the layer stack including a number of levels. A first control gate structure is formed in a first level of the number of levels by: forming a first opening through a dielectric layer of the first level and a sacrificial layer of the first level; removing a remaining portion of the sacrificial layer of the first level to form a first cavity; and disposing a first conductive layer in the first cavity. A second control gate structure is formed in a second level below the first level by: extending the first opening into a dielectric layer of the second level and a sacrificial layer of the second level to form a second opening; removing a remaining portion of the sacrificial layer of the second level to form a second cavity; and disposing a second conductive layer in the second cavity.

Abstract: A transistor device structure may include a submount, a transistor device on the carrier submount, and a metal bonding layer between the submount and the transistor die, the metal bonding stack providing mechanical attachment of the transistor die to the submount. The metal bonding stack may include gold, tin and nickel. A weight percentage of a combination of nickel and tin in the metal bonding layer is greater than 50 percent and a weight percentage of gold in the metal bonding layer is less than 25 percent.

Abstract: Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein at least one termination trench surrounds outer periphery of gate trenches and does not surround the gate metal pad area. The shielded gate electrode inside each of the gate trenches is connected to a source metal through at least one shielded gate trench contact which is spaced apart from at least one gate metal runner with a distance larger than 100 um. A breakdown voltage enhancement region and an avalanche capability enhancement region in the device structures are also disclosed.

Abstract: Fluorescent material composite particles include translucent inorganic particles having a volume average particle diameter in a range of 30 nm or more and 500 nm or less, fluorescent nanoparticles having an average particle diameter in a range of 5 nm or more and 25 nm or less, and a first resin. At least a part of each of the translucent inorganic particles are embedded in the first resin. The translucent inorganic particles are unevenly distributed to a surface of the fluorescent material composite particles. The fluorescent material composite particles have a volume average particle diameter in a range of 0.5 ?m or more and 50 ?m or less.

Abstract: The present disclosure provides a thin film transistor, a display substrate and a display device, and belongs to the field of display technology. The thin film transistor of the present disclosure includes: a base, and a gate, an active layer, a source and a drain located on the base, where the gate includes a first gate and a second gate which are sequentially provided on the base and are electrically connected to each other; the active layer is located between the first gate and the second gate, and orthographic projections of the first gate and the second gate on the base are partially overlapped with an orthographic projection of the active layer on the base, and the orthographic projections of the first gate and the second gate on the base are partially overlapped with each other.

Abstract: A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Abstract: In a display device, light emitting units each formed by stacking a first electrode, an organic layer, and a second electrode are formed in a two-dimensional matrix on a substrate, the first electrode is provided for each light emitting unit, partition walls are formed between adjacent ones of the first electrodes, the organic layer and the second electrode are stacked on the entire surface including a part over the first electrodes and a part over the partition walls, a filling layer filling recesses between the partition walls is formed on the second electrode, the partition walls include stacks each including at least two layers including a lower layer portion on the light emitting unit side and an upper layer portion located above the lower layer portion, and at least part of light entering from the light emitting units is totally reflected on surfaces of the upper layer portions of the partition walls.

Abstract: An enhancement-mode high-electron-mobility transistor comprises a structure including a stack made of III-V semiconductor materials defining an interface and capable of forming a conduction layer in the form of a two-dimensional electron gas layer; a source electrode and a drain electrode forming an electrical contact with the conduction layer; and a gate electrode arranged on top of the structure, between the source electrode and the drain electrode. The structure comprises a bar that is arranged below the gate electrode and passes through the interface of the stack. The bar comprises two semiconductor portions exhibiting opposite types of doping, defining a p-n junction in proximity to the interface.

Abstract: Provided in the present specification are a substrate structure having an exclusive design for allowing assembly on a substrate, at the same time, of a plurality of semiconductor light emitting devices having various colors, and a new type of semiconductor light emitting device, such that the semiconductor light emitting devices can be quickly and accurately assembled on the substrate with a concern about color mixing. Here, at least one of the plurality of semiconductor light emitting devices, according to one embodiment of the present invention, comprises a bump part located in the lateral direction of a surface to be assembled. An assembly groove in which the semiconductor light emitting device including the bump part is assembled is provided with a protrusion part facing toward the inside of the assembly groove.

Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.

Abstract: A display substrate and a preparation method therefor, and a display apparatus are provided. The display substrate includes a display area and a non-display area surrounding the display area, the display area including a first display region, a second display region and a fan-out wiring region, the second display region being located between the first display region and the fan-out wiring region; the first display region including a plurality of first sub-pixels, the first sub-pixel including a first pixel circuit and a first light emitting element; the second display region including a plurality of second sub-pixels, the second sub-pixel including a second pixel circuit and a second light emitting element; the fan-out wiring region including a plurality of data fan-out lines and a plurality of third sub-pixels, the third sub-pixel including a third light emitting element.

Abstract: A display device includes: a substrate including a display area having a plurality of pixel areas and a non-display area surrounding at least one side of the display area; a light-blocking layer disposed on a first surface of the substrate and including light transmissive areas to allow incident light to pass therethrough; a circuit-element layer disposed on the light-blocking layer and including a plurality of conductive layers; a light-emitting element layer disposed on the circuit-element layer and including light-emitting elements; and a sensor layer disposed on a second surface of the substrate opposing the first surface to sense the light passing through the light transmissive areas. The light-blocking layer is electrically coupled to at least one of the plurality of conductive layers.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A semiconductor structure is disclosed. In one example, the semiconductor structure includes: a device region having at least one semiconductor device; a dummy region in contact with the device region; and at least one thermal conductor embedded in the dummy region.