Abstract: Device of the chip or electronic system-in-package type, comprising at least one element for protecting at least part of at least one face of the device, said protective element comprising at least: an attack detection element of the device comprising at least one GMI-effect electrically conductive material, and a magnetic field emitter to which said GMI-effect electrically conductive material is to be subjected, and wherein the GMI effect is to be achieved in said GMI-effect electrically conductive material when an exciting alternating electric current flows therethrough and when subjected to the magnetic field of the magnetic field emitter.

Abstract: The present disclosure provides an array substrate, an electronic device and a manufacturing method of the array substrate. The array substrate includes a base substrate, and a first transistor and a second transistor on the base substrate, a first electrode of the first transistor being connected to a second electrode of the second transistor; the array substrate further includes a photodiode including a first electrode, a second electrode, and a photosensitive layer between the first electrode and the second electrode, and the first electrode is electrically connected to a gate of the first transistor. In the arrangement, the first transistor and the second transistor are connected in series to form one control unit, and the uniformity and stability of the control unit are greatly improved.

Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.

Abstract: An embodiment of the present invention provides an optical film (10) including a light-transmitting base material (11), a hard coat layer (12), and an inorganic layer (13) in this order, wherein the hard coat layer (12) is in contact with the inorganic layer (13), the hard coat layer (12) contains a binder resin (12A) and inorganic particles (12B), the hard coat layer (12) has a film thickness of 1 ?m or more, and the hard coat layer (12) has an indentation hardness of 200 MPa or more.

Abstract: A method of forming an image sensor includes forming a photodiode within a semiconductor substrate. The method further includes disposing an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) over the photodiode; and a plurality of dielectric layers over the CESL, wherein at least one dielectric layer of the plurality of dielectric layers comprises a low dielectric constant (low-k) material. The method further includes patterning at least the plurality of dielectric layers, wherein patterning at least the plurality of dielectric layers comprises defining an opening above an active region of the photodiode. The method further includes depositing a cap layer on sidewalls of the opening, wherein the cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.

Abstract: A display panel, a display apparatus, and a manufacturing method are disclosed. The display panel includes a base substrate having a first through hole; a conductive structure located on the base substrate and at least partially covering the first through hole; and a display structure including a first display structure, a control line, and a second display structure that are arranged in layers on a side of the base substrate where the conductive structure is located, wherein the first display structure has a second through hole, and the control line is electrically connected to the conductive structure by passing through the second through hole.

Abstract: A display panel includes a first base substrate, a plurality of light sources on the first base substrate, a second base substrate opposite to the first base substrate, a light conversion structure on the second base substrate, a plurality of extinction structures on a side of the light conversion structure facing the first base substrate, a first channel formed between any two adjacent extinction structures, a plurality of first optical structures on a side of the light conversion structure facing the first base substrate, wherein the plurality of first optical structures are respectively located in the first channels each between any two adjacent extinction structures, and a filler portion between the plurality of light sources and the plurality of first optical structures. The filler portion contains a material with a refractive index greater than that of a material of the first optical structure, and the extinction structure contains light-absorbing material.

Abstract: A flexible display screen includes: a flexible substrate (1); an OLED device layer (2) formed on the flexible substrate (1); an encapsulation layer(3), disposed on the OLED device layer(2) and encapsulating the OLED device layer (2); and an encapsulation protection layer (4) formed on the encapsulation layer (3). The embodiments of the present disclosure also provide a flexible display device and a manufacturing method of the flexible display screen.

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract: A light emitting diode (LED) device comprises: an interposer comprising: an interposer body, a plurality of pillars on a first surface of the interposer body, and two or more local fiducials on the first surface of the interposer body; an LED die comprising a die body and a first die surface comprising a plurality of light emitting diodes (LEDs), the LED die being mounted on the plurality of pillars; and a flux material located between each of the pillars and a second die surface of the die body, the second die surface of the die body being opposite the first die surface, there being no flux material on a fiducial surface of each of the local fiducials. Methods of manufacturing a light emitting diode (LED) devices comprise: printing a flux material onto the pillars of the interposer, attaching an LED die to the pillars, and washing away excess flux material.

Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a substrate and an array layer disposed on a side of the substrate; a light-emitting layer, where the light-emitting layer is on a side of the array layer away from the substrate and includes a plurality of light-emitting units; and a color filter layer. The color filter layer includes a light-blocking portion and a plurality of color resist units; the plurality of color resist units is disposed corresponding to the plurality of light-emitting units; at least two color resist units of a same color have different orthographic projection shapes on a same first plane; a first plane at least includes one of a first sub-plane and a second sub-plane; the first sub-plane is a plane perpendicular to the substrate; and the second sub-plane is a plane in parallel with the substrate.

Abstract: An imaging device that generates, in a pixel, a potential higher than a potential to be supplied to the pixel is provided. The imaging device includes a pixel including a first circuit and a second circuit; the second circuit includes a photoelectric conversion device; the first circuit is electrically connected to the second circuit; the first circuit has a function of adding a first potential and a second potential to generate a third potential; and the second circuit has a function of generating data in the photoelectric conversion device to which the third potential is applied and has a function of outputting the data.

Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity-type; a bottom surface electrode to which a first potential is applied, the bottom surface electrode being provided on a bottom surface of the semiconductor base body; a first well of a second conductivity-type to which a second potential lower than the first potential is applied, the first well being provided on a top surface side of the semiconductor base body; a second well of the first conductivity-type provided in the first well; and an edge structure provided in the first well and configured to supply a third potential higher than the second potential to the second well.

Abstract: A method of forming an optoelectronic semiconductor device involves providing an amorphous substrate. A transparent and conductive oxide layer is deposited on the amorphous substrate. The transparent and conductive oxide layer is annealed to form an annealed transparent and conductive oxide layer having a cubic-oriented and/or rhombohedral-oriented surface. A nanorod array is formed on the cubic-oriented and/or rhombohedral-oriented surface of the annealed transparent and conductive oxide layer. The annealing of the transparent conductive oxide layer and the formation of the nanorod array are performed using molecular beam epitaxy (MBE). The nanorods of the nanorod array comprise a group-III material and are non-polar.

Abstract: A cell of fluidic assembly of microchips on a substrate, including: a base having its upper surface intended to receive the substrate; a body laterally delimiting a fluidic chamber above the substrate; and a cover closing the fluidic chamber from its upper surface, wherein the body comprises first and second nozzles respectively emerging onto opposite first and second lateral edges of the fluidic chamber, each of the first and second nozzles being adapted to injecting and/or sucking in a liquid suspension of microchips into and/or from the fluidic chamber, in a direction parallel to the mean plane of the substrate.

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.

Abstract: A high-voltage switch, whose operation leverages the speed of electrons to generate the “on” time of the pulse in combination with the speed of light to generate the “off” time of the pulse, is described. In one example, the high-voltage switch includes a first electrode, a second electrode spaced apart from the first electrode, a region of non-absorbing material occupying a portion of the space between the first and second electrodes and allowing a laser pulse to propagate therethrough without substantial absorption, and a region of absorbing material occupying another portion of the space and producing a charged particle cloud upon receiving the laser pulse. The high-voltage switch remains “on” upon the charged particle cloud reaching an electrode and until it has been collected by the electrode, and where the high-voltage switch remains “off” subsequent to the collection and until another generated charged particle cloud reaches the electrode.

Abstract: A display device and method of manufacturing same includes: a display panel having a pixel area and a peripheral area adjacent to the pixel area, a light control layer disposed on the display panel and at least partially overlapping the pixel area, a light blocking portion at least partially overlapping the peripheral area, and a protective layer disposed between the light control layer and the light blocking portion.

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.