Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape.

Abstract: Reinforcing material having Rockwell hardness of 60 or above and comprising base material and adhesive is formed, and then the reinforcing material is attached to one side of silicon wafer on which circuits are not formed prior to dicing.

Abstract: A thin nitrode film having a low resistance is formed at a low film-forming temperature. In the step of forming a thin nitride film of a high temperature-melting point metal by introducing a feedstock gas having the high temperature-melting point metal and a reductive nitrogen-containing gas having a nitrogen atom into a vacuum atmosphere; an auxiliary reductive gas free from nitrogen is also introduced. The high temperature-melting point metal deposited due to the auxiliary reductive gas compensates for the deficiency of the high temperature-melting point metal of the deposited nitride; and thus enable the growth of the thin nitride film having a low resistance.

Abstract: A process for fabricating a microelectromechanical optical component from a silicon substrate is disclosed. The component comprises optical propagation guides; a wall which can move with respect to the propagation guides; and an electrostatic actuator associated with return means formed by at least one beam capable of causing the moving wall to move with respect to the rest of the substrate. The substrate is single-crystal silicon having (111) crystallographic planes parallel to the plane of the substrate. The process comprises a first series of deep reactive ion etching steps during which the heights of the moving wall, of the electrodes of the actuator, and of the beams of the return means of the actuator are defined with different values, and a second wet etching step, making it possible to free the moving wall, the electrodes and the beams from the rest of the substrate.

Abstract: The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the device without affecting the performance of the active circuits. The bonding pad structure is composed of at least two metal layers overlying the active circuits so that the bonding pad may be subjected to thermal and mechanical stresses without damaging the underlying active circuits. The metal layer underlying the bonding pad is patterned and etched forming an array of openings in the metal that may take any shape, e.g. slots, grid, circles. The present invention enables a reduction in the chip area and eliminates the parasitic resistance due to long interconnection wires between bonding pads and active regions.

Abstract: A spin dependent tunneling (“SDT”) junction of a memory cell for a Magnetic Random Access Memory (“MRAM”) device includes a pinned ferromagnetic layer, followed by an insulating tunnel barrier and a sense ferromagnetic layer. During fabrication of the MRAM device, after formation of the pinned layer but before formation of the insulating tunnel barrier, an exposed surface of the pinned layer is flattened. The exposed surface of the pinned layer may be flattened by an ion etching process.

Abstract: A semiconductor device includes a substrate forming a trench, the trench including a storage node disposed within the trench. A wordline is disposed within the substrate and adjacent to a portion of the substrate. A vertically disposed transistor is included wherein the wordline functions as a gate, the storage node and a bitline function as one of a source and a drain such that when activated by the wordline the transistor conducts between the storage node and the bitline. The invention further includes a method of fabricating the semiconductor device with vertical transistors.

Abstract: The present invention provides a micromechanical or microoptomechanical structure. The structure is produced by a process comprising defining a structure on a single crystal silicon layer separated by an insulator layer from a substrate layer; depositing and etching a polysilicon layer on the single crystal silicon layer, with remaining polysilcon forming mechanical or optical elements of the structure; exposing a selected area of the single crystal silicon layer; and releasing the formed structure.

Abstract: A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices.

Abstract: The optoelectronic component has a radiation-receiving or radiation-emitting semiconductor chip mounted on a base part. The chip is contacted with at least two electrode terminals made of an electrically conductive connection material. The electrode terminals are formed by a thin coating, which is deposited on the outer surfaces of the base part, is applied by electrodeposition and is patterned by means of laser etching.

Abstract: A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure of the active device, and first and second electrodes are provided inside a mesa structure provided for the resistance element with a separation from a sidewall of the mesa structure, the first and second electrodes being formed in correspondence to openings formed in the dummy pattern.

Abstract: A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area.

Abstract: A method of manufacturing a microlens array substrate is provided comprising the steps of: closely providing a substrate precursor (30) between a first master mold (10) having a plurality of curved surfaces (12) and a second master mold (20) having a plurality of projections (22) to form a substrate (32) having a plurality of lenses (34) formed by the curved surfaces (12) and recesses (36) formed by the projections (22); removing the first and second master molds (10, 20) from the substrate (32); and filling the recesses (36) with a shading material (42) after the second master mold (20) is removed.

Abstract: An array substrate for use in an X-ray sensing device is fabricated using an etching stopper that enables good control of the etching process and that prevents over-etch of drain electrodes and second capacitor electrodes while forming contact holes and a cutting furrow. The etching stopper is located in a tiling portion that is utilized for tiling substrates to form a large-sized X-ray detector. During fabrication, gate lines can have gate-protruded portions located near the etching stopper, and the etching stopper can have stopper-protruded portions near the gate lines. The stopper-protruded portions electrically connect to the gate-protruded portions through gate line contact holes such that the etching stopper and the gate lines have equipotentials. This can reduce static electricity damage.

Abstract: An apparatus for enclosing logic chips includes a substrate upon which a logic chip is mounted and a mold cap disposed upon the substrate and covering the logic chip. The mold cap includes at least one extension of sufficient size and shape to provide structural support to a corner section of the substrate.

Abstract: A semiconductor device having an array of dummy interconnections in a fuse window are proposed. The each dummy interconnection comprised of a fuse body scheduled to be blown away by laser beam, a fuse wiring extended up to the bottom of the fuse body from one side of the fuse window, and another fuse wiring extended up to the bottom of the fuse body form the another side of the fuse window. Contact plugs are disposed on terminal portions of the fuse wirings respectively, the terminal portions facing to each other having a predetermined gap between them. The bottom surfaces of both terminal portions of the fuse body are electrically connected with the facing terminal portions of the fuse wirings through the contact plugs, respectively. The length of the fuse body is set so as to have a length not shorter than the predetermined gap and not exceeding a diameter of laser beam to blow off the fuse body.

Abstract: Ions of arsenic are selectively implanted at a high concentration into a substrate through a first passivation film of silicon dioxide to obtain a shallow junction, thereby forming a source region with a low resistivity and a first drain region. Then, after the first passivation film is removed, a second passivation film of silicon dioxide is deposited over the substrate as well as over a stacked cell electrode by a CVD process performed at a relatively low temperature. Thereafter, the substrate is annealed in a nitrogen ambient at such a temperature as activating the dopant introduced. In this manner, the dopant in source region and first drain region is activated.

Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.