Abstract: A computer system provides a vector monitor for monitoring a first instance of an error-handling vector in architected memory. The monitoring can involve repeatedly comparing the first instance with a second instance of the vector so as to detect a mismatch, should it occur. If a mismatch is detected, the vector monitor can notify an administrator, automatically initiate diagnostic routines, and/or correct the mismatch. As a result, potential fatal events in which firmware confronts a corrupted error-handling vector are less likely to occur.

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

Abstract: A storage system and method for handling bad storage device data therefor are described. The present invention uses a first mark and/or a second mark for the data processing of the redundant storage devices when the storage system is in the degraded mode together with a media error occurred or when in data writing, there is a reading abnormality in the storage devices so that new check data cannot be generated; and therefore, a better data protection method is provided.

Abstract: A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.

Abstract: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

Abstract: A system for selective self-healing of memory errors comprises a processor coupled to a memory, where the memory stores instructions executable by the processor to store an error record for each memory management error detected during an execution of the application. The error record identifies an allocation location (e.g., a portion of a stack trace corresponding to the invocation of a memory allocation function such as malloc( )) of an object associated with the memory management error. The instructions are executable to use the error record to identify, during subsequent execution, memory operations performed on objects allocated from the allocation location, and to perform corresponding memory protection operations (e.g., operations to prevent re-occurrences of the memory errors) for the memory operations identified using the error record.

Abstract: A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol.

Abstract: The failure management sections of a host computer and a storage unit are connected through a failure reporting interface. When a failure occurs in the storage unit, the failure information is notified from the failure management section of the storage unit to the failure management section of the host computer through the failure reporting interface, and the failure management section of the host computer deletes the failure information detected by software in the host computer based on the failure information from the storage unit. In this manner, the management of the failure information in the storage system can be unified by the service processor of the host computer. Consequently, it becomes possible to determine whether a failure generated in a host computer is a secondary failure or tertiary failure and to show the defect part indicating information minimum necessary for the maintenance and replacement.